
CDB4226
DS188DB1
43
SW1 SWITCH #
6, 5
0 = closed, 1 = open
MCLK_S1, MCLK_S0 Divides CLKOUT to generate MCLK_8402 for CS8402A transmitter.
0 0
Generates a 128 Fs clock when CLKOUT = 256 Fs (CO = 0).
0 1
RESERVED
1 0
Generates a 128 Fs clock when CLKOUT = 384 Fs (CO = 1).
1 1
Generates a 128 Fs clock when CLKOUT = 512 Fs (CO = 2).
SP_RISING
Selects SCLK valid data edge. This bit must agree with DSCK bit in
DSP Port Mode Byte.
0
Data is clocked into CS8402A on falling edge of SCLK (DSCK = 1).
1
Data is clocked into CS8402A on rising edge of SCLK (DSCK = 0).
SP_L_RB
Selects left or right justified data. This bit must agree with DDF bits in
DSP Port Mode Byte.
0
Serial data lines are right justified (DDF = 0,1,2).
1
Serial data lines are left justified (DDF
≠
0,1,2).
BITS1, BITS0
Selects bits of resolution. These bits must agree with DDF bits in DSP
Port Mode Byte.
0 0
16 bits (DDF = 2)
0 1
18 bits (DDF = 1)
1 0
20 bits (DDF = 0, 3)
1 1
RESERVED
0 = closed, 1 = open
I
2
S
DSP Port Mode Byte.
0
I
2
S mode off (DDF
≠
4).
1
I
2
S mode on (DDF = 4).
SDOUT_M0
Selects the source of data to the CS8402A.
0
SDOUT1 from CS4226 is routed to SDATA pin of CS8402A.
1
SDOUT2 from CS4226 is routed to SDATA pin of CS8402A.
SDIN_M2, SDIN_M1,
SDIN_M0
are SDOUT lines from the CS4226, SDIN lines from DSP_HDR, or
zeros.
0 0 0
SDOUT1 => SDIN1, 0 => SDIN2, 0 => SDIN3
0 0 1
0 => SDIN1, SDOUT1 => SDIN2, 0 => SDIN3
0 1 0
0 => SDIN1, 0 => SDIN2, SDOUT1 => SDIN3
0 1 1
SDOUT1 => SDIN1, SDOUT1 => SDIN2, SDOUT1 => SDIN3
1 0 0
SDOUT2 => SDIN1, SDOUT2 => SDIN2, SDOUT2 => SDIN3
1 0 1
SDOUT1 => SDIN1, SDOUT1 => SDIN2, SDOUT2 => SDIN3
1 1 0
SDOUT1 => SDIN1, SDOUT2 => SDIN2, SDOUT2 =>SDIN3
1 1 1
SDIN1_HDR =>SDIN1, SDIN2_HDR =>SDIN2, SDIN3_HDR =>SDIN3
Table 3. DIP Switch Definitions
Comment
4
3
2, 1
S2 SWITCH #
Comment
5
Selects I
2
S compatible mode. This bit must agree with DDF bits in
4
3, 2, 1
Selects the source of data to SDIN1, 2, and 3 on the CS4226. Choices