參數(shù)資料
型號(hào): CDB4226
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: Surround Sound Codec
中文描述: 環(huán)繞聲編解碼器
文件頁(yè)數(shù): 22/60頁(yè)
文件大?。?/td> 1619K
代理商: CDB4226
CS4226
22
DS188F1
Converter Control Byte (02h)
RS
Chip reset (Do not clear this bit until all registers have been configured as desired)
0 - No Reset
1 - Reset
CAL
Calibration control bit
0 - Normal operation
1 - Rising edge initiates calibration
LC
Loop Current
0 - Normal Mode, 25
μ
A PLL loop current (See Figure 1 for filter component values)
1 - High Current Mode, 300
μ
A PLL loop current (See Figure 1 for filter component values)
The following bits are read only:
AUTO
AC3 and MPEG Automatic Detection
0 - No AC3/MPEG Detected
1 - AC3/MPEG detected on RX/AUX
DU
Shows selected De-Emphasis setting used by DAC’s
0 - Normal Flat DAC frequency response
1 - De-Emphasis selected
CLKE
Clocking system status
0 - No errors
1 - PLL is not locked, crystal is not oscillating, or requesting clock change in progress
CALP
Calibration status
1 - Calibration in progress
0 - Calibration doneThis register defaults to 01h
This register defaults to 01h
NOTE: The AC3 and MPEG detection for the AUTO bit does not look at the channel status bits. This bit is deter-
mined by looking for the AC3/MPEG header in the data stream. See the “AC3/MPEG Auto Detection” section earlier
in the datasheet for more details.
DAC Control Byte (03h)
MUT6-MUT1
Mute control bits
0 - Normal output level
1 - Selected DAC output muted
MUTC
Controls mute on consecutive zeros function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros
ZCD
Zero crossing disable
0 - DAC mutes and volume control changes occur on zero-crossings.
1 - DAC mutes and volume control changes occur immediately.
This register defaults to 3Fh.
B7
B6
B5
DU
B4
B3
LC
B2
0
B1
CAL
B0
RS
CALP
CLKE
AUTO
B7
ZCD
B6
B5
B4
B3
B2
B1
B0
MUTC
MUT6
MUT5
MUT4
MUT3
MUT2
MUT1
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