參數(shù)資料
型號： CDB4226
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： Surround Sound Codec
中文描述： 環(huán)繞聲編解碼器
文件頁數(shù)： 19/60頁
文件大?。?/td> 1619K
代理商： CDB4226
CS4226
DS188F1
19
HOLD Function
If the digital audio source presents invalid data to
the CS4226, the CS4226 may be configured to
cause the last valid digital input sample to be held
constant. Holding the previous output sample oc-
curs when the user asserts the HOLD pin
(HOLD=1) at any time during the stereo sample pe-
riod, or if a parity, biphase, or validity error occurs
when receiving S/PDIF data. Parity, biphase, and
validity errors can be independently masked so that
no hold occurs. This is done using the VM, PM, and
BM bits in the Input Control Byte. During a HOLD
condition, AUXPort (S/PDIF) input data is ig-
nored.
DAC outputs can be automatically muted after an
extended HOLD period (>15 samples) by setting
the MOH (Mute On Hold) bit = 0 in the Auxiliary
Port Control Byte. DACs will not be automatically
muted when MOH=1. When the S/PDIF error con-
dition is removed or the HOLD pin is de-asserted
(HOLD=0), the DAC outputs will return to one of
two different states controlled by the UMV (Un-
mute on Valid Data) bit in the Auxiliary Port Con-
trol Byte. When UMV=0, the DAC outputs will
unmute when the error is removed. When UMV=1,
the DACs must be unmuted in the DAC Control
Byte after the error is removed. This allows the user
to unmute the DAC after the invalid data has
passed through the DSP.
Power Supply, Layout, and Grounding
As with any high resolution converter, the CS4226
requires careful attention to power supply and
grounding arrangements to optimize performance.
Figure 1 shows the recommended power arrange-
ment with VA connected to a clean +5V supply.
VD should be derived from VA through a 2 ohm re-
sistor. VD should not be used to power additional
circuitry. Pins 18, 20, 39 and 41, AGND and
DGND should be connected together at the
CS4226. DGND for the CS4226 should not be
confused with the ground for the digital section of
the system. The CS4226 should be positioned over
the analog ground plane near the digital/analog
ground plane split. The analog and digital ground
planes must be connected elsewhere in the system.
The CS4226 evaluation board, CDB4226, demon-
strates this layout technique. This technique mini-
mizes digital noise and insures proper power
supply matching and sequencing. Decoupling ca-
pacitors for VA, VD, and CMOUT should be locat-
ed as close to the device package as possible. See
Crystal’s Application Note AN018: Layout and De-
sign Rules for Data Converters and Other Mixed
Signal Devices, and the CDB4226 evaluation
board data sheet for recommended layout of the de-
coupling components.
The CS4226 will mute the analog outputs and enter
the Power Down Mode if the supply drops below
approximately 4 volts.
ADC and DAC Filter Response Plots
Figures 10 through 15 show the overall frequency
response, passband ripple and transition band for
the CS4226 ADC’s and DAC’s.
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