參數(shù)資料
型號(hào)： CDB4226
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： Surround Sound Codec
中文描述： 環(huán)繞聲編解碼器
文件頁(yè)數(shù)： 16/60頁(yè)
文件大?。?/td> 1619K
代理商： CDB4226
CS4226
16
DS188F1
high, these bytes are being updated and may be in-
valid. Additionally, the audio/non-audio, AC-
3/MPEG data stream indicator and sampling fre-
quency channel status bits may be output to pins 9,
10, 11 and 12, respectively, see Table 4. This is ac-
complished by setting the CSP bit to 1 in the Aux-
iliary Status Output Byte. The FREQ0/1 channel
status bit outputs are decoded from the sampling
frequency channel status bits after first referencing
channel status byte 0, bit 0 (PRO or consumer bit)
which indicates the appropriate location of these
bits in the channel status data stream.
The received user bit is output on the HOLD/RU-
BIT pin if the HPC bit in the AUX Port Control
Byte is set to 1. It can be sampled with the rising or
falling edge of LRCK if the audio DSP port is in
Master Mode.
AC-3/MPEG Auto Detection
For AC-3/MPEG applications, it is important to
know whether the incoming S/PDIF data stream is
digital audio or compressed AC-3/MPEG data.
This information is typically conveyed by setting
channel status bit 1 (audio/non-audio bit), but some
AC-3/MPEG sources may not strictly adhere to this
convention and the bit may not be properly set. The
CS4226 S/PDIF receiver has the capability to auto-
matically detect whether the incoming data is a
compressed AC-3/MPEG input. This is accom-
plished by looking for an AC-3/MPEG 96-bit sync
code consisting of six 16-bit words. The 96-bit
sync code consists of: 0x0000, 0x0000, 0x0000,
0x0000, 0xF872, and 0x4E1F. When the sync code
is detected, the AUTODATA indicator (pin 10)
will go high. If no additional sync codes are detect-
ed within the next 4096 frames, the AUTODATA
indicator pin will return low until another sync
code is detected.
Control Port Signals
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference
problems, the control port pins should remain static
if no operation is required.
The control port has 2 modes: SPI and I
2
C, with the
CS4226 as a slave device. The SPI mode is selected
by setting the I
2
C/SPI pin low, and I
2
C is selected
by setting the I
2
C/SPI pin high. The state of this
pin is continuously monitored.
SPI Mode
In SPI mode, CS is the CS4226 chip select signal,
CCLK is the control port bit clock, (input into the
CS4226 from the microcontroller), CDIN is the in-
put data line from the microcontroller, CDOUT is
the output data line to the microcontroller, and the
chip address is 0010000. Data is clocked in on the
rising edge of CCLK and out on the falling edge.
Figure 7 shows the control port timing in SPI mode.
To write to a register, bring CS low. The first 7 bits
on CDIN form the chip address, and they must be
0010000. The eighth bit is a read/write indicator
(R/W), which should be low to write. The next 8
bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to
be updated. The next 8 bits are the data which will
be placed into register designated by the MAP.
During writes, the CDOUT output stays in the high
impedance state. It may be externally pulled high
or low with a 47 k
resistor.
The CS4226 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is a zero, then the MAP will stay constant for
AUDIO
Pin 9
0 - Audio data
1 - Non-audio data
0 - No preamble detected in
last 4096 frames
1 - Preamble detected
00 - 44.1 kHz
01 - 48 kHz
10 - Reserved
11 - 32 kHz
AUTODATA Pin 10
FREQ0/1
Pin 11/12
Table 4. S/PDIF Receiver Status Outputs
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