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參數(shù)資料
| 型號： | CDB4225 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Digital Audio Conversion System |
| 中文描述： | 數(shù)字音頻轉(zhuǎn)換系統(tǒng) |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 385K |
| 代理商： | CDB4225 |
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Reset
RST-PDN going low causes all the internal con-
trol registers, used in software mode, to be set to
the states indicated in Table 1. The reset states
are different for hardware mode, see the section
on Hardware Mode. RST-PDN must be brought
low and high at least once after power up. RST-
PDN returning high causes the CS4225 to
execute an offset calibration cycle. RST-PDN re-
turning high should occur at least 50ms after the
power supply has stabilized.
Power Down Mode
Placing the RST-PDN pin into a high impedance
state (floating) puts the CS4225 into the power
down mode. This may be done by driving the
RST-PDN pin with a three-state buffer, and set-
ting the buffer to the hi-z state. In power-down
mode CMOUT and VREF will not supply cur-
rent. If the master clock source stops, the
CS4225 will power down after 5
μ
s. Power down
will change all the control registers to the reset
state shown in Table 1.
After returning to normal operation from power
down, an offset calibration cycle must be exe-
cuted. To leave the power-down state, pull
RST-PDN low for at least 50ms to allow the in-
ternal voltage reference time to settle, then high
to initiate an offset calibration cycle.
De-Emphasis
Figure 8 shows the de-emphasis curve. De-em-
phasis may be enabled under hardware control,
using the DEM pin, or by software control using
the DEM bit. In software mode, either hardware
or software control of de-emphasis may be se-
lected.
The de-emphasis corner frequencies are as
shown in Figure 8 for a sample rate of 44.1kHz.
Selection of de-emphasis at other sample rates
will cause the filter to be applied, but with cor-
ner frequencies scaled proportionally to the
sample rate.
Hold Function (Software Mode only)
If the digital audio source has an invalid data
output pin, then the CS4225 may be configured
to cause the last valid analog output level to be
held constant. (This sounds much better than a
potentially random output level.) HOLD is sam-
pled on the active edge of SCLK. If HOLD is
driven high any time during the stereo sample
period, both pairs of DAC’s hold their current
output level, and reject the data currently being
input. SDIN input data is ignored while the
HOLD pin is high. For normal operation, the
HOLD pin must be low.
ATT6
→
ATT0
GN4
→
GN0
ADF1, ADF0
ACK1, ACK0
AMS
DDF2
→
DDF0
DCK1, DCK1
DMS
MAP
CAL
= 127
= 0
= 0
= 0
= 1
= 0
= 0
= 1
= 0
= 0
CS2, CS1,CS0 = 3
CI1, CI0
CO1, CO0
MUT4
→
MUT1 = 1111
DEM
DEMC
MUTC
IS1, IS0
AIM
= 0
= 0
= 0
= 0
= 0
= 0
= 0
Table 1 - Reset State (Software Mode)
* with Fs = 44.1 kHz
Gain
dB
-10dB
0dB
Frequency
T2 = 15us*
T1=50us*
F1
F2
(0.072 Fs)
(0.241 Fs)
Figure 8 - De-emphasis Curve.
CS4225
DS86PP8
19
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