參數(shù)資料
型號(hào)： CDB4225
廠商： Cirrus Logic, Inc.
英文描述： Digital Audio Conversion System
中文描述： 數(shù)字音頻轉(zhuǎn)換系統(tǒng)
文件頁(yè)數(shù)： 18/30頁(yè)
文件大?。?/td> 385K
代理商： CDB4225
B7
B6
CO1
B5
CO0
B4
CI1
B3
CI0
B2
CS2
B1
CS1
B0
CS0
0
CS1 - CS0
Sets the source of the master clock
which runs the CS4225.
0 - Crystal Oscillator or XTI (PLL Disabled)
1 - PLL driven by LRCKAUX at 1 Fs
2 - PLL driven by LRCK at 1 Fs
3 - PLL driven by XTI/XTO (XTI at 1 Fs)
4 - PLL driven by SCLK at 32 Fs
5 - PLL driven by SCLK at 64 Fs
6 - PLL driven by SCLKAUX at 32 Fs
7 - PLL driven by SCLKAUX at 64 Fs
Determines frequency of XTI
when PLL is disabled.
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - Reserved
Determines CLKOUT frequency
0 - 256 Fs
1 - 384 Fs
2 - 512 Fs
3 - 1 Fs
Cl1 - CI0
CO1-CO0
Clock Mode Byte (9)
B7
MUTC CAL DEMC DEM MUT4 MUT3 MUT2 MUT1
B6
B5
B4
B3
B2
B1
B0
MUT4 to
MUT1
Mute Control Bits
0 - Normal Output Level
1 - Selected DAC output muted
Selects De-Emphasis
0 - Normal Flat DAC frequency response
1 - CD De-Emphasis Selected
Selects De-Emphasis Control Source
0 - De-emphasis is controlled by DEM
pin. DEM bit is ignored.
1 - De-emphasis is controlled by DEM bit.
DEM pin is ignored.
0 - Normal Operation
1 - Initiate Calibration
Controls mute on consecutive zeros
function
0 - 512 consecutive zeros will mute DAC
1 - DAC output will not mute on zeros.
DEM
DEMC
CAL
MUTC
B7
OVL1 OVL0 OV12 ACK
B6
B5
B4
B3
0
B2
B1
B0
0
LOCK CALD
OVL1 to
OVL0
16 - bit ADC overload bits.
00 - Normal ADC input levels
01 - -6 dB level
10 - -3 dB level
11 - Clipping
Indicates one of the ADC’s has been
overdriven. These bits are "sticky".
They will stay set until read, when they
will return to 00 if the overload is no
longer present.
12-bit ADC overload bit
0 - normal input
1 - clipped input
This bit is also "sticky"
Control port data check bit
0 - Multiple of 8 clocks received
last word (SPI Mode)
1 - Error, not multiple of 8 clocks received.
PLL lock indicator
0 - PLL not locked. If PLL is selected,
DAC outputs will mute
1 - PLL locked
0 - Calibration done
1 - Calibration in progress
OV12
ACK
LOCK
CALD
Status Report Byte (11)
B7
B6
0
B5
0
B4
0
B3
0
B2
0
B1
IS1
B0
IS0
0
IS1 - IS0
Select input channel
0 - Select AIN1
1 - Select AIN2
2 - Select AIN3
3 - Select Auxiliary Digital Input Port
Input Selection Byte (12)
B7
AIM
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
AIM
Auxiliary Input Mode Control Bit
0 - AINAUX signal is routed to 12-bit ADC
1 - AINAUX routed to AINL of 16-bit ADC
Aux Control Byte (13)
Control Byte (10)
CS4225
18
DS86PP8
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參數(shù)描述
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