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參數(shù)資料
| 型號： | CDB4225 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Digital Audio Conversion System |
| 中文描述： | 數(shù)字音頻轉(zhuǎn)換系統(tǒng) |
| 文件頁數(shù)： | 15/30頁 |
| 文件大?。?/td> | 385K |
| 代理商： | CDB4225 |
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Auxiliary Audio Port Signals
The auxiliary port provides an alternate way to
input digital audio signals into the CS4225, and
allows the CS4225 to synchronize the system to
an external digital audio source. This port con-
sists of clock, data and left/right clock pins
named,
SCLKAUX,
LRCKAUX. These signals are fed through to the
SCLK, SDOUT1 and LRCK pins. There is a two
frame delay from DATAAUX to SDOUT1.
When the auxiliary port is used, the frequency of
LRCKAUX must equal to the system sample
rate, Fs, but no particular phase relationship is
required.
DATAAUX
and
Auxiliary Audio Port Formats
Input data on DATAAUX is clocked into the part
by SCLKAUX using the format selected in the
Auxiliary Port Mode Byte. In hardware mode,
the auxiliary port format is the same as the DSP
port format and is determined by the DIF pin.
The auxiliary audio port supports the same 4 for-
mats as the audio DSP port in 2 data line mode.
LRCKAUX is used to indicate left and right data
samples, and the start of a new sample period.
SCLKAUX and LRCKAUX may be output from
the CS4225, or they may be generated from an
external source, as set by the AMS control bit in
Software mode or IF1 in Hardware mode.
Control Port Signals
The control port has 2 modes: SPI and I
2
C
,
with the CS4225 as a slave device. The SPI
mode is selected by setting the H/S pin low.
I
2
C
mode is selected by floating the H/S pin.
If the H/S pin is floated, add a 0.1
μ
F capacitor
to ground on the H/S pin to minimize noise
pickup.
SPI Mode
In SPI mode, CS is the CS4225 chip select sig-
nal, CCLK is the control port bit clock, (input
into the CS4225 from the microcontroller),
CDIN is the input data line from the microcon-
troller, CDOUT is the output data line to the
microcontroller, and AD0 and AD1 form the
chip address.
The pins AD0, AD1 must be tied to one of 4
possible chip addresses. To write to a particular
CS4225, the AD0, AD1 bits must match the state
of the AD0, AD1 pins for that chip. This allows
up to 4 CS4225 devices to co-exist on one con-
trol port bus.
Figure 6 shows the operation of the control port
in SPI mode. To write to a register, bring CS
low. The first 5 bits on CDIN must be zero. The
next 2 bits form the chip address. The eighth bit
is a read/write indicator (R/W), which should be
MAP
MSB
LSB
DATA
byte 1
byte n
R/W
AD1
AD0
0
R/W
AD1
AD0
High Z
MAP = Memory Address Pointer
ADDRESS
CHIP
ADDRESS
CHIP
0
CDIN
CCLK
CS
CDOUT
MSB
LSB
MSB
LSB
Figure 6 - Control Port Timing, SPI mode
CS4225
DS86PP8
15
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