參數(shù)資料
型號: CDB4224
廠商: Cirrus Logic, Inc.
元件分類: Codec
英文描述: 24-Bit 105 dB Audio Codec with Volume Control
中文描述: 24位105分貝的音量控制音頻編解碼器
文件頁數(shù): 8/32頁
文件大小: 778K
代理商: CDB4224
CS4223 CS4224
8
DS290PP3
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (CS4224)
(T
A
= 25° C; VA, VD = 4.75 V - 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VD; C
L
= 30 pF)
Notes: 11.
Not tested but guaranteed by design.
t
spi
only needed before first falling edge of CS after RST rising edge. t
spi
= 0 at all other times.
Data must be held for sufficient time to bridge the transition time of CCLK.
For F
SCK
< 1 MHz.
12.
13.
14.
Parameter
Symbol
Min
Max
Unit
SPI Mode (SPI/I2C = 0)
CCLK Clock Frequency
f
sck
t
srs
t
spi
t
csh
t
css
t
scl
t
sch
t
dsu
t
dh
t
r2
t
f2
-
6
MHz
RST rising edge to CS falling
(Note 11)
41
-
μs
CCLK edge to CS falling
(Note 12)
500
-
ns
CS High Time between transmissions
1.0
-
μs
CS falling to CCLK edge
20
-
ns
CCLK Low Time
66
-
ns
CCLK High Time
66
-
ns
CDIN to CCLK rising setup time
40
-
ns
CCLK rising to DATA hold time
(Note 13)
15
-
ns
Rise time of CCLK and CDIN
(Note 14)
-
100
ns
Fall time of CCLK and CDIN
(Note 14)
-
100
ns
tr2
tf2
tdsu
tdh
tsch
tscl
CS
CCLK
CDIN
tcss
tcsh
tspi
tsrs
RST
Figure 2. SPI Control Port Timing
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