- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379828 > CDB4223 (Cirrus Logic, Inc.) 24-Bit 105 dB Audio Codec with Volume Control PDF資料下載
參數(shù)資料
| 型號： | CDB4223 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 24-Bit 105 dB Audio Codec with Volume Control |
| 中文描述： | 24位105分貝的音量控制音頻編解碼器 |
| 文件頁數(shù)： | 20/32頁 |
| 文件大?。?/td> | 778K |
| 代理商： | CDB4223 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
CS4223 CS4224
20
DS290PP3
7.
PIN DESCRIPTIONS — CS4224
1
2
3
4
5
6
7
8
9
10
11
12
13
14
21
20
22
23
24
25
26
27
28
NC
RST
AOUTL-
AOUTL+
AOUTR+
AOUTR-
AGND
VA
AINL+
SDOUT
SDIN
DGND
VD
SCLK
LRCK
XTI
XTO
NC
17
16
18
19
AINL-
I2C/SPI
AINR+
AINR-
NC
AD0/CS
SDA/CDIN
SCL/CCLK
15
NC
VL
CS4224
NC
1,14,15, 28
No Connect -
These pins are not connected internally and should be tied to DGND to mini-
mize noise coupling.
XTI, XTO
2,3
Crystal Connections (Input/Output) -
Input and output connections for the crystal used to
clock the CS4224. Alternatively a clock may be input into XTI. This is the clock source for the
delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x,
or 512x Fs. The default XTI setting in Master Mode is 256x, but this may be changed to 384x
or 512x through the Control Port.
LRCK
4
Left/Right Clock (Input) -
Determines which channel is currently being input/output of the
serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the
input sample rate. Although the outputs for each ADC channel are transmitted at different
times, Left/Right pairs represent simultaneously sampled analog inputs. The required relation-
ship between the left/right clock, serial clock and serial data is defined by the DSP Port Mode
(05h) register. The options are detailed in Figures 8 - 11.
SCLK
5
Serial Data Clock (Input) -
Clocks the individual bits of the serial data into the SDIN pin and
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and
serial data is defined by the DSP Port Mode (05h) register. The options are detailed in Figures
8 - 11.
VD
6
Digital Power (Input) -
Positive power supply for the digital section. Typically 5.0 VDC.
DGND
7
Digital Ground (Input) -
Digital ground for the digital section.
Fs (kHz)
XTI (MHz)
384x
12.2880
16.9344
18.4320
256x
8.1920
11.2896
12.2880
512x
16.3840
22.5792
24.5760
32
44.1
48
Table 5. Common Clock Frequencies
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4225 | Digital Audio Conversion System |
| CDB4226 | Surround Sound Codec |
| CDB4228A | 24-Bit, 96 kHz Surround Sound Codec |
| CDB4228 | 24-Bit, 96 kHz Surround Sound Codec |
| CDB42416 | 110 dB, 192kHz 6-Ch CODEC WITH PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4224 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4225 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Digital Audio Conversion System |
| CDB4226 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Surround Sound Codec |
| CDB4227 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Six Channel, 20-Bit Codec |
| CDB4228 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit, 96 kHz Surround Sound Codec |
發(fā)布緊急采購，3分鐘左右您將得到回復。