參數(shù)資料
型號(hào): CDB4223
廠商: Cirrus Logic, Inc.
元件分類(lèi): Codec
英文描述: 24-Bit 105 dB Audio Codec with Volume Control
中文描述: 24位105分貝的音量控制音頻編解碼器
文件頁(yè)數(shù): 16/32頁(yè)
文件大?。?/td> 778K
代理商: CDB4223
CS4223 CS4224
16
DS290PP3
5.5
DSP Port Mode (address 05h)
5.5.1
DE-EMPHASIS CONTROL (DEM)
Default = 00
00 - 44.1 kHz de-emphasis setting
01 - 48 kHz de-emphasis setting
10 - 32 kHz de-emphasis setting
11 - De-emphasis disabled
Function:
Selects the appropriate digital filter to maintain the standard 15
μ
s/50
μ
s digital de-emphasis filter re-
sponse at 32, 44.1 or 48 kHz sample rates, see Figure 15.
5.5.2
SERIAL INPUT/OUTPUT DATA SCLK POLARITY SELECT (DSCK)
Default = 0
0 - Data valid on rising edge of SCLK
1 - Data valid on falling edge of SCLK
Function:
This function selects the polarity of the SCLK edge used to clock data in and out of the serial audio
port.
5.5.3
SERIAL DATA OUTPUT FORMAT (DOF)
Default = 00
00 - I
2
S compatible
01 - Left justified
10 - Right justified, 24-bit
11 - Right justified, 20-bit
Function:
The required relationship between the left/right clock, serial clock and output serial data is defined by
the Serial Data Output Format, and the options are detailed in Figures 8-11.
Note: If the format selected is Right-Justified, SCLK must be 64 Fs when operating in slave mode.
5.5.4
SERIAL DATA INPUT FORMAT (DIF)
Default = 00
00 - I
2
S compatible
01 - Left justified
10 - Right justified, 24-bit
11- Right justified, 20-bit
Function:
The required relationship between the left/right clock, serial clock and input serial data is defined by
the Serial Data Input Format, and the options are detailed in Figures 8-11.
7
6
5
4
3
2
1
0
Reserved
0
DEM1
0
DEM0
0
DSCK
0
DOF1
0
DOF0
0
DIF1
0
DIF0
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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