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參數(shù)資料
| 型號： | CDB4222 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo Audio Codec with Volume Control |
| 中文描述： | 20帶有音量位立體聲音頻編解碼器控制 |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 580K |
| 代理商： | CDB4222 |
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Control Port Signals
SCL/CCLK - Serial Control Interface Clock, Pin 10.
SCL/CCLK is the serial control interface clock and is used to clock control bits into and out of
the CS4222 This pin should be tied to DGND in stand-alone mode.
AD0/CS - Address Bit/Control Port Chip Select, Pin 12.
In I
2
C mode, AD0 is a chip address bit. In SPI mode, CS is used to enable the control port
interface on the CS4222. The CS4222 will enter SPI mode if a negative transition is ever seen
on this pin after power up. This pin should be tied to DGND in stand-alone mode.
SDA/CDIN - Serial Control Data In, Pin 11.
SDA/CDIN is the input data line for the control port interface. This pin should be tied to
DGND in stand-alone mode.
Miscellaneous Pins
RST - Reset, Pin 27.
When low, the CS4222 enters a low power mode and all internal states are reset, including the
control port. When high, the control port becomes operational and normal operation will occur.
NC - No Connect, Pins 1, 14, 15 and 28
These pins are not connected internally and should be tied to DGND to minimize noise
coupling.
PARAMETER DEFINITIONS
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral
components over the specified bandwidth. Dynamic range is a signal-to-noise measurement
over the specified bandwidth made with a -60dBFS signal. 60dB is then added to the resulting
measurement to refer the measurement to full scale. This technique ensures that the distortion
components are below the noise level and do not affect the measurement. This measurement
technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic
Industries Association of Japan, EIAJ CP-307.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over
the specified bandwidth (typically 20Hz to 20kHz), including distortion components. Expressed
in decibels. ADCs are measured at -1 dBFS as suggested in AES17-1991 Annex A and DACs
are measured at 0 dBFS.
CS4222
DS236PP3
23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4224 | 24-Bit 105 dB Audio Codec with Volume Control |
| CDB4223 | 24-Bit 105 dB Audio Codec with Volume Control |
| CDB4225 | Digital Audio Conversion System |
| CDB4226 | Surround Sound Codec |
| CDB4228A | 24-Bit, 96 kHz Surround Sound Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4223 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4224 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4225 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Digital Audio Conversion System |
| CDB4226 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Surround Sound Codec |
| CDB4227 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Six Channel, 20-Bit Codec |
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