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參數(shù)資料
| 型號： | CDB4222 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 20-Bit Stereo Audio Codec with Volume Control |
| 中文描述： | 20帶有音量位立體聲音頻編解碼器控制 |
| 文件頁數(shù)： | 15/26頁 |
| 文件大小： | 580K |
| 代理商： | CDB4222 |
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not supported in the SPI mode. The next 8 bits
form the Memory Address Pointer (MAP), which
is set to the address of the register that is to be
updated. The next 8 bits are the data which will
be placed into register designated by the MAP.
The CS4222 has a MAP auto increment capabil-
ity, enabled by the INCR bit in the MAP register.
If INCR is a zero, then the MAP will stay con-
stant for successive writes. If INCR is set to a 1,
then MAP will auto increment after each byte is
written, allowing block writes of successive reg-
isters. Register reading from the CS4222 is not
supported in the SPI mode.
I
2
C
Mode
In I
2
C
mode, SDA is a bidirectional data line.
Data is clocked into and out of the part by the
clock, SCL, with the clock to data relationship as
shown in Figure 9. There is no CS pin. Pin AD0
forms the partial chip address and should be tied
to VD or DGND as desired. The upper 6 bits of
the 7 bit address field must be 001000. To com-
municate with the CS4222 the LSB of the chip
address field, which is the first byte sent to the
CS4222, should match the setting of the AD0
pin. The eighth bit of the address byte is the
R/W bit (high for a read, low for a write). If the
operation is a write, the next byte is the Memory
Address Pointer which selects the register to be
read or written. If the operation is a read, the
contents of the register pointed to by the Mem-
ory Address Pointer will be output. Setting the
auto increment bit in MAP, allows successive
reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit. Use of
the I
2
C bus
compatible interface requires a li-
cense from Philips. I
2
C bus
is a registered
trademark of Philips Semiconductor.
Control Port Bit Definitions
All registers can be written and read in I
2
C
mode, except the Converter Status Report Byte
(#6) and the CLKE and CALP bits in the ADC
control byte (#1) which are read only. SPI mode
only allows for register writing. See the follow-
ing bit definition tables for bit assignment
information.
SDA
SCL
001000
ADDR
AD0
R/W
Start
ACK
DATA
1-8
ACK
DATA
1-8
ACK
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 9. Control Port Timing, I
2
C
Mode
Note 1
CS4222
DS236PP3
15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4224 | 24-Bit 105 dB Audio Codec with Volume Control |
| CDB4223 | 24-Bit 105 dB Audio Codec with Volume Control |
| CDB4225 | Digital Audio Conversion System |
| CDB4226 | Surround Sound Codec |
| CDB4228A | 24-Bit, 96 kHz Surround Sound Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4223 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4224 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4225 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Digital Audio Conversion System |
| CDB4226 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Surround Sound Codec |
| CDB4227 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Six Channel, 20-Bit Codec |
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