參數(shù)資料
型號(hào)： CDB4221
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 24-Bit Stereo Audio Codec with 3V Interface
中文描述： 24位立體聲音頻編解碼器接口為3V
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 770K
代理商： CDB4221
CS4220 CS4221
18
DS284PP3
6.
PIN DESCRIPTIONS — CS4220
14
21
20
22
23
24
25
26
27
NC
SDOUT
SDIN
VD
SCLK
LRCK
XTI
XTO
NC
17
16
19
18
DEM0
DIF0
DIF1
15
NC
VL
CS4220
1
2
3
4
5
6
7
8
9
10
11
12
13
28
NC
RST
AOUTL-
AOUTL+
AOUTR+
AOUTR-
AGND
VA
AINL+
AINL-
DEM1
AINR+
AINR-
DGND
NC
1,14,15, 28
No Connect -
These pins are not connected internally and should be tied to DGND to mini-
mize noise coupling.
XTI, XTO
2,3
Crystal Connections (Input/Output) -
Input and output connections for the crystal used to
clock the CS4220. Alternatively, a clock may be input into XTI. This is the clock source for the
delta-sigma modulator and digital filters. The frequency of this clock must be either 256x, 384x,
or 512x Fs in Slave Mode and 256x in Master Mode.
LRCK
4
Left/Right Clock (Input) -
Determines which channel is currently being input/output of the
serial audio data pins SDIN/SDOUT. The frequency of the Left/Right clock must be equal to the
input sample rate. Although the outputs for each ADC channel are transmitted at different
times, Left/Right pairs represent simultaneously sampled analog inputs. The required relation-
ship between the left/right clock, serial clock and serial data is defined by the DIF1-0 pins. The
options are detailed in Figures 8 - 11.
SCLK
5
Serial Data Clock (Input) -
Clocks the individual bits of the serial data into the SDIN pin and
out of the SDOUT pin. The required relationship between the left/right clock, serial clock and
serial data is defined by the DIF1-0 pins. The options are detailed in Figures 8 - 11.
VD
6
Digital Power (Input) -
Positive power supply for the digital section. Typically 5.0 VDC.
DGND
7
Digital Ground (Input) -
Digital ground for the digital section.
SDOUT
8
Serial Data Output (Output) -
Two’s complement MSB-first serial data is output on this pin.
The required relationship between the left/right clock, serial clock and serial data is defined by
the DIF1-0 pins. The options are detailed in Figures 8 - 11.
SDIN
9
Serial Data Input (Input) -
Two’s complement MSB-first serial data is input on this pin. The
required relationship between the left/right clock, serial clock and serial data is defined by the
DIF1-0 pins. The options are detailed in Figures 8 - 11.
Fs (kHz)
XTI (MHz)
384x
12.2880
16.9344
18.4320
256x
8.1920
11.2896
12.2880
512x
16.3840
22.5792
24.5760
32
44.1
48
Table 2. Common Clock Frequencies
相關(guān)PDF資料
PDF描述
CDB4222 20-Bit Stereo Audio Codec with Volume Control
CDB4224 24-Bit 105 dB Audio Codec with Volume Control
CDB4223 24-Bit 105 dB Audio Codec with Volume Control
CDB4225 Digital Audio Conversion System
CDB4226 Surround Sound Codec
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB4222 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:20-Bit Stereo Audio Codec with Volume Control
CDB4223 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control
CDB4224 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control
CDB4225 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Digital Audio Conversion System
CDB4226 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Surround Sound Codec
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