參數(shù)資料
型號(hào): CDB4220
廠商: Cirrus Logic, Inc.
元件分類(lèi): Codec
英文描述: 24-Bit Stereo Audio Codec with 3V Interface
中文描述: 24位立體聲音頻編解碼器接口為3V
文件頁(yè)數(shù): 7/32頁(yè)
文件大小: 770K
代理商: CDB4220
CS4220 CS4221
DS284PP3
7
SWITCHING CHARACTERISTICS
(T
A
= 25° C; VA, VD = 4.75 V - 5.25 V; outputs loaded with
30 pF)
Notes: 10.
After powering up the CS4220/1, PDN should be held low for 10 ms to allow the power supply to settle.
Parameter
Symbol
Fs
Min
4
1.024
13
21
31
13
21
31
-
10
-
-
25
25
Typ
-
-
-
-
-
-
-
-
500
-
-
-
-
-
-
-
-
-
-
Max
50
26
-
-
-
-
-
-
-
-
Unit
kHz
MHz
ns
Audio ADC’s and DAC’s Sample Rate
XTI Frequency
XTI Pulse Width High
XTI = 256, 384, or 512 Fs
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI = 512 Fs
XTI = 384 Fs
XTI = 256 Fs
XTI Pulse Width Low
ns
XTI Jitter Tolerance
RST Low Time
SCLK falling edge to SDOUT output valid
LRCK edge to MSB valid
SDIN setup time before SCLK rising edge
SDIN hold time after SCLK rising edge
SCLK Period
SCLK High Time
SCLK Low Time
SCLK rising to LRCK edge
LRCK edge to SCLK rising
psRMS
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note 10)
DSCK = 0
t
dpd
t
lrpd
t
ds
t
dh
t
sckw
t
sckh
t
sckl
t
lrckd
t
lrcks
45
-
-
-
-
-
-
-
DSCK = 0
DSCK = 0
40
40
35
40
DSCK = 0
DSCK = 0
(384) Fs
20
+
(128) Fs
sckh
sckl
sckw
t
t
t
MSB
MSB-1
*SCLK shown for DSCK = 0, SCLK inverted for DSCK = 1.
tdpd
SDOUT
LRCK
SCLK*
SDIN
dh
t
ds
t
lrpd
t
lrcks
t
lrckd
t
Figure 1. Serial Audio Port Data I/O Timing
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