參數(shù)資料
型號： CDB4220
廠商： Cirrus Logic, Inc.
元件分類： Codec
英文描述： 24-Bit Stereo Audio Codec with 3V Interface
中文描述： 24位立體聲音頻編解碼器接口為3V
文件頁數(shù)： 23/32頁
文件大?。?/td> 770K
代理商： CDB4220
CS4220 CS4221
DS284PP3
23
Once RST goes high, the control port is functional
and the desired settings should be loaded.
The CS4220/1 will also enter power down mode if
the master clock source stops for approximately
10 μs or if the LRCK is not synchronous to the
master clock. The control port will retain its current
settings.
The CS4220/1 will mute the analog outputs and en-
ter the power down mode if the supply drops below
approximately 4 volts.
8.8
The control port is used to load all the internal set-
tings. The operation of the control port may be
completely asynchronous with the audio sample
rate. However, to avoid potential interference prob-
lems, the control port pins should remain static if
no operation is required.
The control port has 2 modes: SPI
and I
2
C
, with
the CS4221 operating as a slave device. The con-
trol port interface format is selected by the SPI/I2C
pin.
Control Port Interface (CS4221 only)
8.8.1
SPI Mode
In SPI mode, CS is the CS4221 chip select signal,
CCLK is the control port bit clock, CDIN is the in-
put data line from the microcontroller and the chip
address is 0010000. All signals are inputs and data
is clocked in on the rising edge of CCLK.
Figure 6 shows the operation of the control port in
SPI mode. To write to a register, bring CS low. The
first 7 bits on CDIN form the chip address, and
must be 0010000. The eighth bit is a read/write in-
dicator (R/W), which must be low to write. Regis-
ter reading from the CS4221 is not supported in the
SPI mode. The next 8 bits form the Memory Ad-
dress Pointer (MAP), which is set to the address of
the register that is to be updated. The next 8 bits are
the data which will be placed into a register desig-
nated by the MAP.
The CS4221 has a MAP auto increment capability,
enabled by the INCR bit in the MAP register. If
INCR is a zero, then the MAP will stay constant for
successive writes. If INCR is set to a 1, then MAP
will auto increment after each byte is written, al-
lowing block writes of successive registers. Regis-
ter reading from the CS4221 is not supported in the
SPI mode.
8.8.2
In I
2
C mode, SDA is a bidirectional data line. Data
is clocked into and out of the part by the clock,
SCL, with the clock to data relationship as shown
in Figure 7. There is no CS pin. Pin AD0 forms the
partial chip address and should be tied to VD or
DGND as desired. The upper 6 bits of the 7 bit ad-
dress field must be 001000. In order to communi-
cate with the CS4221, the LSB of the chip address
field (first byte sent to the CS4221) should match
the setting of the AD0 pin. The eighth bit of the ad-
dress byte is the R/W bit (high for a read, low for a
write). If the operation is a write, the next byte is
the Memory Address Pointer which selects the reg-
ister to be read or written. If the operation is a read,
the contents of the register pointed to by the Mem-
ory Address Pointer will be output. Setting the auto
increment bit in MAP, allows successive reads or
writes of consecutive registers. Each byte is sepa-
rated by an acknowledge bit.
I
2
C Mode
相關(guān)PDF資料
PDF描述
CDB4221 24-Bit Stereo Audio Codec with 3V Interface
CDB4222 20-Bit Stereo Audio Codec with Volume Control
CDB4224 24-Bit 105 dB Audio Codec with Volume Control
CDB4223 24-Bit 105 dB Audio Codec with Volume Control
CDB4225 Digital Audio Conversion System
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CDB4221 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface
CDB4222 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:20-Bit Stereo Audio Codec with Volume Control
CDB4223 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control
CDB4224 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control
CDB4225 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Digital Audio Conversion System
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