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參數(shù)資料
| 型號： | CDB4216 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 16-Bit Stereo Audio Codec |
| 中文描述： | 16位立體聲音頻編解碼器 |
| 文件頁數(shù)： | 23/58頁 |
| 文件大小： | 799K |
| 代理商： | CDB4216 |
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per frame, Master sub-mode) reduces the DSP
interrupts in half since the control data is split
from the audio data. This circuit is comprised of
three independent sections which may individu-
ally be eliminated if not needed.
To load control data into the codec, three
HC597’s are utilized. These are both latches that
store the DSP-sent control data, and shift regis-
ters that shift the data into the codec. The codec
uses an inverted SSYNC signal to copy the
latches to the shift registers every frame. In this
diagram the DSP is assumed to have a data bus
bandwidth of at least 24 bits. If the DSP has less
than 24_bits, the three HC597s must be split into
two addresses. Since the HC597 internal latches
are copied to the shift registers, the latches con-
tinually hold the DSP-sent data; therefore, the
DSP only needs to write data to the latches when
a change is desired.
The second section is comprised of an HC595
shift register and latch that is clocked by an in-
verted SCLK The data shifted into the HC595 is
transferred to the HC595’s latch by the SSYNC
signal. This HC595 captures the 8 bits prior to
the SSYNC signal (which is also MF4:CCS) go-
ing high. As shown in Figure 14, and assuming
the MF4:CCS (SSYNC) signal rises at bit 32,
the 8-bits prior to MF4:CCS rising are a copy of
all the important status bits. This allows one shift
register to capture all the important information.
The interrupt pin cannot reliably be used in this
configuration since the interrupt pin is cleared by
reading the control port which occurs asynchro-
Micro-
Controller
Serial
Port
General
Purpose
Port
Pins
IRQ
DSP
SDOUT
SDIN
SSYNC
SCLK
CS4216
MF1:CDOUT
MF2:CDIN
MF4:CCS
MF3:CCLK
RESET
MF8:F3
MF7:F2
MF6:F1
MF5:INT
SM4
VD+
43
42
1
44
40
39
36
35
38
2
34
31
30
Figure 15. SM4 - Microcontroller Interface
DSP
SDOUT
SDIN
SSYNC
SCLK
CS4216
SM4
32 BPF
MF1:CDOUT
MF2:CDIN
MF4:CCS
MF3:CCLK
MF5:INT
VD+
RESET
MF8:F3
MF7:F2
MF6:F1
Hard Wired or
DIP Switch
selectable
43
42
1
44
35
36
38
40
39
2
34
31
30
Figure 16. SM4 - Minimum DSP Interface
CS4216
DS83F2
23
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4220 | 24-Bit Stereo Audio Codec with 3V Interface |
| CDB4221 | 24-Bit Stereo Audio Codec with 3V Interface |
| CDB4222 | 20-Bit Stereo Audio Codec with Volume Control |
| CDB4224 | 24-Bit 105 dB Audio Codec with Volume Control |
| CDB4223 | 24-Bit 105 dB Audio Codec with Volume Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4220 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CDB4221 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CDB4222 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:20-Bit Stereo Audio Codec with Volume Control |
| CDB4223 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
| CDB4224 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
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