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參數(shù)資料
| 型號： | CDB4215 |
| 廠商： | Cirrus Logic, Inc. |
| 元件分類： | Codec |
| 英文描述： | 16-Bit Multimedia Audio Codec |
| 中文描述： | 16位多媒體音頻編解碼器 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大小： | 878K |
| 代理商： | CDB4215 |
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of 128 (80 Hex) is considered analog zero for
the 8-bit unsigned format.
A non-linear coding scheme is used for the com-
panded formats as shown in Figure 14
.
This
scheme is compatible with CCITT G.711. Com-
panding uses more precision at lower amplitudes
at the expense of less precision at higher ampli-
tudes.
μ
-Law is equivalent to 13 bits at low
signal levels and A-Law is equivalent to 12 bits.
This low-level dynamic range is obtained at the
expense of large-signal dynamic range which, for
both
μ
-Law and A-Law, is equivalent to 6 bits.
The CS4215 internally operates at 16 bits. The
companded data is expanded to the upper 13
(12) bits for the DACs and compressed from the
upper 13 (12) bits to 8 bits for the ADCs.
Data Time Slot 1&2, Left Channel Audio Data
Time slot 1 and 2 contain audio data for the left
channel. In mono modes, only the left channel
data is used, however both the right and left
output DACs are driven. In 8-bit modes, only
time slot 1 is used for the data.
Data Time Slot 3&4, Right Channel Audio Data
Time slot 3 and 4 contains audio data for the
right channel. In mono modes, the right ADC
outputs zero and the right DAC uses the left
digital data. In 8-bit modes, only time slot 3 is
used for the data.
Figure 15 summarizes all the time slot bit alloca-
tions for the 4 data modes and for control mode.
Reset
RESET going low causes all the internal control
registers to be set to the states shown with each
register description. RESET must be brought low
and high at least once after power up. RESET
returning high causes the CS4215 to execute an
offset calibration cycle. RESET or D/C returning
high should occur at least 50 ms after the power
supply has stabilized to allow the voltage refer-
ence to settle.
Data Time Slot 5, Output Setting
D7
HE
0
D6
LE
0
D5
LO5 LO4 LO3 LO2 LO1 LO0
1
1
1
D4
D3
D2
D1
D0
1
1
1
Register
Reset (R)
BIT
NAME
VALUE
FUNCTION
LO5-0
Left Channel Output
Attenuation Setting
Line Output Enable
1 1 1 1 1 1
63 R 1.5dB attenuation steps. LO5 is the MSB.
0 = no attenuation. 111111 = -94.5dB
R Analog line outputs off (muted).
Analog line outputs on.
R Headphone output off (muted).
Headphone output on.
LE
0
1
0
1
HE
Headphone Output
Enable
0
+FS
-FS
DIGITAL CODE
A
A-Law: 2Ah
u-Law:
15h
3Fh
95h
BFh
AAh
80h
7Fh/FFh
55h/D5h
00h
Figure 14. Companded Data Formats
CS4215
22
DS76F2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDB4216 | 16-Bit Stereo Audio Codec |
| CDB4220 | 24-Bit Stereo Audio Codec with 3V Interface |
| CDB4221 | 24-Bit Stereo Audio Codec with 3V Interface |
| CDB4222 | 20-Bit Stereo Audio Codec with Volume Control |
| CDB4224 | 24-Bit 105 dB Audio Codec with Volume Control |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDB4216 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-Bit Stereo Audio Codec |
| CDB4220 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CDB4221 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit Stereo Audio Codec with 3V Interface |
| CDB4222 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:20-Bit Stereo Audio Codec with Volume Control |
| CDB4223 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:24-Bit 105 dB Audio Codec with Volume Control |
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