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參數(shù)資料
| 型號(hào)： | CD82C85 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | CMOS Static Clock Controller/Generator |
| 中文描述： | 24 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP24 |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 363K |
| 代理商： | CD82C85 |
312
FIGURE 13. RESET TIMING (CLK RUNNING WITH F/C LOW-OSC MODE)
(CLK RUNNING-OR STOPPED WITH F/C HIGH EFI MODE)
FIGURE 14. RESET TIMING (OSCILLATOR STOPPED, F/C LOW)
NOTE: CLK, CLK50, PCLK Remain in the High State until RES goes high and 8192 valid oscillator cycles have been registered by the 82C85
internal counter (TOST time period). After RES goes high and CLK, CLK50, PCLK become active, the RESET output will remain high
for minimum of 16 CLK cycles (TRST).
Timing Waveforms
(Continued)
RES
CLK
RESET
(21) TSHSL
(17)
TI1HCL
(36)
TCLIL
(42)
TRST
(36)
TCLIL
(17)
TI1HCL
RES
(21) TSHSL
CLK
RESET
OSCILLATOR
STARTUP
TIME
X1
(39)
TOST
8192
CYCLES
(42)
TRST
(36)
TCLIL
82C85
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