參數(shù)資料
型號(hào)： CD82C59A-5
廠商： HARRIS SEMICONDUCTOR
元件分類(lèi)： 中斷控制器
英文描述： CMOS Priority Interrupt Controller
中文描述： 80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800 COMPATIBLE, INTERRUPT CONTROLLER, CDIP28
文件頁(yè)數(shù)： 14/20頁(yè)
文件大?。?/td> 152K
代理商： CD82C59A-5
4-14
This modification forces the use of software programming to
determine whether the 82C59A is a master or a slave. Bit 3
in ICW4 programs the buffered mode, and bit 2 in lCW4
determines whether it is a master or a slave.
Cascade Mode
The 82C59A can be easily interconnected in a system of
one master with up to eight slaves to handle up to 64 priority
levels.
The master controls the slaves through the 3 line cascade
bus (CAS2 - 0). The cascade bus acts like chip selects to the
slaves during the INTA sequence.
In a cascade configuration, the slave interrupt outputs (INT)
are connected to the master interrupt request inputs. When
a slave request line is activated and afterwards acknowl-
edged, the master will enable the corresponding slave to
release the device routine address during bytes 2 and 3 of
INTA. (Byte 2 only for 80C86/88/286).
The cascade bus lines are normally low and will contain the
slave address code from the leading edge of the first INTA
pulse to the trailing edge of the last INTA pulse. Each
82C59A in the system must follow a separate initialization
sequence and can be programmed to work in a different
mode. An EOI command must be issued twice: once for the
master and once for the corresponding slave. Chip select
decoding is required to activate each 82C59A.
NOTE: Auto EOI is supported in the slave mode for the 82C59A.
The cascade lines of the Master 82C59A are activated only
for slave inputs, non-slave inputs leave the cascade line
inactive (low). Therefore, it is necessary to use a slave
address of 0 (zero) only after all other addresses are used.
FIGURE 11. CASCADING THE 82C59A
CS
82C59A
SLAVE A
CINT
CAS 1
CAS 2
1
A
0
D
7
- D
0
INTA
SP/EN 7
5
6
4
3
2
0
GND
7
5
6
4
3
2
1
0
CS
82C59A
SLAVE B
CINT
CAS 1
CAS 2
1
A
0
D
7
- D
0
INTA
SP/EN 7
5
6
4
3
2
0
GND
7
5
6
4
3
2
1
0
CS
MASTER 82C59A
CAS 0
CAS 1
CAS 2
SP/EN 7
INT
A
0
D
7
- D
0
INTA
5
6
4
3
2
1
0
V
CC
7
5
4
2
1
0
3
6
INT REQ
DATA BUS (8)
CONTROL BUS
ADDRESS BUS (16)
INTERRUPT REQUESTS
82C59A
相關(guān)PDF資料
PDF描述
CD82C59A-12 CMOS Priority Interrupt Controller
CD82C82 CMOS Octal Latching Bus Driver
CD82C83H CMOS Octal Latching Inverting Bus Driver
CD82C84A CMOS Clock Generator Driver
CD82C85 CMOS Static Clock Controller/Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CD82C59AB5984 制造商:Rochester Electronics LLC 功能描述:- Bulk
CD82C82 制造商:Rochester Electronics LLC 功能描述:- Bulk
CD82C83H 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Octal Latching Inverting Bus Driver
CD82C84A 制造商:INTERSIL 制造商全稱(chēng):Intersil Corporation 功能描述:CMOS Clock Generator Driver
CD82C85 制造商:Rochester Electronics LLC 功能描述:- Bulk
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