參數(shù)資料
型號(hào)： CD74HC4046APWTG4
廠(chǎng)商： Texas Instruments
文件頁(yè)數(shù)： 30/34頁(yè)
文件大?。?/td> 0K
描述： IC PLL W/VCO 16-SSOP
標(biāo)準(zhǔn)包裝： 250
系列： 74HC
類(lèi)型： 鎖相環(huán)路（PLL）
PLL： 是
輸入： CMOS
輸出： CMOS
電路數(shù)： 1
比率 - 輸入:輸出： 1:4
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 38MHz
除法器/乘法器： 無(wú)/無(wú)
電源電壓： 2 V ~ 6 V
工作溫度： -55°C ~ 125°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 16-TSSOP
包裝： 帶卷 (TR)
5
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in three-state and the VCO
input at pin 9 is a high impedance. Also in this condition,
the signal at the phase comparator pulse output (PCPOUT)
is a HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between SIGIN
and COMPIN over the full frequency range of the VCO.
Moreover, the power dissipation due to the low-pass lter is
reduced because both p- and n-type drivers are “OFF” for
most of the signal input cycle. It should be noted that the
PLL lock range for this type of phase comparator is equal to
the capture range and is independent of the low-pass lter.
With no signal present at SIGIN, the VCO adjusts, via PC2,
to its lowest frequency.
Phase Comparator 3 (PC3)
This
is
a
positive
edge-triggered
sequential
phase
detector using an RS-type flip-flop. When the PLL is using
this comparator, the loop is controlled by positive signal
transitions and the duty factors of SIGIN and COMPIN are
not
important.
The
transfer
characteristic
of
PC3,
assuming ripple (fr = fi) is suppressed, is:
VDEMOUT =(VCC/2p) (fSIGIN - fCOMPIN) where
VDEMOUT is the demodulator output at pin 10; VDEMOUT
= VPC3OUT (via low-pass filter).
The average output from PC3, fed to the VCO via the low-
pass filter and seen at the demodulator at pin 10
(VDEMOUT), is the resultant of the phase differences of
SIGIN and COMPIN as shown in Figure 6. Typical
waveforms for the PC3 loop locked at fo are shown in
Figure 7.
The
phase-to-output
response
characteristic
of
PC3
(Figure 6) differs from that of PC2 in that the phase angle
between SIGIN and COMPIN varies between 0
o and 360o
and is 180o at the center frequency. Also PC3 gives a
greater voltage swing than PC2 for input phase differences
but as aconsequence the ripple content of the VCO input
signal is higher. With no signal present at SIGIN, the VCO
adjusts, via PC3, to its highest frequency.
The only difference between the HC and HCT versions is the
input level specication of the INH input. This input disables
the VCO section. The comparator’s sections are identical, so
that there is no difference in the SIGIN (pin 14) or COMPIN
(pin 3) inputs between the HC and the HCT versions.
FIGURE 6. PHASE COMPARATOR 3: AVERAGE OUTPUT
VOLTAGE vs INPUT PHASE DIFFERENCE:
VDEMOUT = VPC3OUT
= (VCC/2π) (φSIGIN - φCOMPIN);
φDEMOUT = (φSIGIN - φCOMPIN)
VCC
VDEMOUT (AV)
1/2 VCC
0
0o
180o
φ
DEMOUT
360o
FIGURE 7. TYPICAL WAVEFORMS FOR PLL USING PHASE
COMPARATOR 3, LOOP LOCKED AT fo
SIGIN
COMPIN
VCOOUT
PC3OUT
VCOIN
VCC
GND
CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A
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