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  • 參數(shù)資料
    型號(hào): CAT25C65LI-1.8TE13
    英文描述: 32K/64K-Bit SPI Serial CMOS EEPROM
    中文描述: 32K/64K-Bit SPI串行EEPROM中的CMOS
    文件頁(yè)數(shù): 1/11頁(yè)
    文件大?。?/td> 90K
    代理商: CAT25C65LI-1.8TE13
    CAT25C33/65
    32K/64K-Bit SPI Serial CMOS EEPROM
    FEATURES
    I
    10 MHz SPI compatible
    I
    1.8 to 6.0 volt operation
    I
    Hardware and software protection
    I
    Low power CMOS technology
    I
    SPI modes (0,0 &1,1)
    I
    Commercial, industrial, automotive and extended
    temperature ranges
    I
    1,000,000 program/erase cycles
    I
    100 year data tetention
    I
    Self-timed write cycle
    I
    8-pin DIP/SOIC and 14-pin TSSOP
    I
    64-byte page write buffer
    I
    Block write protection
    – Protect first page, last page, any 1/4 or lower
    1/2 of EEPROM array
    PIN CONFIGURATION
    SOIC Package (S, V)
    PIN FUNCTIONS
    Pin Name
    Function
    SO
    Serial Data Output
    SCK
    Serial Clock
    WP
    Write Protect
    V
    CC
    +1.8V to +6.0V Power Supply
    V
    SS
    Ground
    CS
    Chip Select
    SI
    Serial Data Input
    HOLD
    Suspends Serial Input
    NC
    No Connect
    BLOCK DIAGRAM
    2004 by Catalyst Semiconductor, Inc.
    Characteristics subject to change without notice
    DESCRIPTION
    The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS
    EEPROM internally organized as 4Kx8/8Kx8 bits.
    Catalyst’s advanced CMOS Technology substantially
    reduces device power requirements. The CAT25C33/
    65 features a 64-byte page write buffer. The device
    operates via the SPI bus serial interface and is enabled
    though a Chip Select (
    CS
    ). In addition to the Chip Select,
    the clock input (SCK), data in (SI) and data out (SO) are
    required to access the device. The
    HOLD
    pin may be
    used to suspend any serial communication without
    resetting the serial sequence. The CAT25C32/64 is
    designed with software and hardware write protection
    features including Block write protection. The device is
    available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and
    20-pin TSSOP packages.
    Doc No. 1000, Rev. F
    DIP Package (P, L)
    SENSE AMPS
    SHIFT REGISTERS
    SPI
    CONTROL
    LOGIC
    WORD ADDRESS
    BUFFERS
    I/O
    CONTROL
    E
    2
    PROM
    ARRAY
    COLUMN
    DECODERS
    XDEC
    HIGH VOLTAGE/
    TIMING CONTROL
    SO
    SI
    STATUS
    REGISTER
    BLOCK
    PROTECT
    LOGIC
    C
    DATA IN
    STORAGE
    CS
    WP
    HOLD
    SCK
    SO
    WP
    VSS
    CS
    VCC
    HOLD
    SCK
    SI
    1
    2
    3
    4
    8
    7
    6
    5
    VSS
    SO
    WP
    VCC
    HOLD
    SCK
    SI
    1
    2
    3
    4
    8
    7
    6
    5
    CS
    TSSOP Package (U14, Y14)
    CS
    SO
    NC
    WP
    V
    SS
    HOLD
    NC
    NC
    NC
    SCK
    SI
    VCC
    NC
    NC
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    H
    A
    L
    O
    G
    E
    N
    F
    R
    E
    E
    TM
    L
    E
    A
    D
    F
    R
    E
    E
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