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參數(shù)資料
| 型號(hào)： | CA3130E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output |
| 中文描述： | OP-AMP, 15000 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDIP8 |
| 文件頁(yè)數(shù)： | 5/15頁(yè) |
| 文件大?。?/td> | 654K |
| 代理商： | CA3130E |
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5
through D
8
provide gate-oxide protection against high-voltage
transients, including static electricity during handling for Q
6
and Q
7
.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q
11
and its cascade-connected load resistance provided by
PMOS transistors Q
3
and Q
5
. The source of bias potentials
for these PMOS transistors is subsequently described. Miller
Effect compensation (roll-off) is accomplished by simply
connecting a small capacitor between Terminals 1 and 8. A
47pF capacitor provides sufficient compensation for stable
unity-gain operation in most applications.
Bias-Source Circuit
At total supply voltages, somewhat above 8.3V, resistor R
2
and zener diode Z
1
serve to establish a voltage of 8.3V across
the series-connected circuit, consisting of resistor R
1
, diodes
D
1
through D
4
, and PMOS transistor Q
1
. A tap at the junction
of resistor R
1
and diode D
4
provides a gate-bias potential of
about 4.5V for PMOS transistors Q
4
and Q
5
with respect to
Terminal 7. A potential of about 2.2V is developed across
diode-connected PMOS transistor Q
1
with respect to Terminal
7 to provide gate bias for PMOS transistors Q
2
and Q
3
. It
should be noted that Q
1
is “mirror-connected (see Note 8)” to
both Q
2
and Q
3
. Since transistors Q
1
, Q
2
, Q
3
are designed to
be identical, the approximately 200
μ
A current in Q
1
establishes a similar current in Q
2
and Q
3
as constant current
sources for both the first and second amplifier stages,
respectively.
At total supply voltages somewhat less than 8.3V, zener
diode Z
1
becomes nonconductive and the potential,
developed across series-connected R
1
, D
1
-D
4
, and Q
1
,
varies directly with variations in supply voltage.
Consequently, the gate bias for Q
4
, Q
5
and Q
2
, Q
3
varies in
accordance with supply-voltage variations. This variation
results in deterioration of the power-supply-rejection ratio
(PSRR) at total supply voltages below 8.3V. Operation at
total supply voltages below about 4.5V results in seriously
degraded performance.
Output Stage
The output stage consists of a drain-loaded inverting
amplifier using CMOS transistors operating in the Class A
mode. When operating into very high resistance loads, the
output can be swung within millivolts of either supply rail.
Because the output stage is a drain-loaded amplifier, its gain
is dependent upon the load impedance. The transfer
characteristics of the output stage for a load returned to the
negative supply rail are shown in Figure 2. Typical op amp
loads are readily driven by the output stage. Because large-
signal excursions are non-linear, requiring feedback for good
waveform reproduction, transient delays may be
encountered. As a voltage follower, the amplifier can achieve
0.01% accuracy levels, including the negative supply rail.
NOTE:
8. For general information on the characteristics of CMOS transis-
tor-pairs in linear-circuit applications, see File Number 619, data
sheet on CA3600E “CMOS Transistor Array”.
Input Current Variation with Common Mode Input
Voltage
As shown in the Table of Electrical Specifications, the input
current for the CA3130 Series Op Amps is typically 5pA at
T
A
= 25
o
C when Terminals 2 and 3 are at a common-mode
potential of +7.5V with respect to negative supply Terminal 4.
Figure 3 contains data showing the variation of input current
as a function of common-mode input voltage at T
A
= 25
o
C.
3
2
-
7
4
8
1
5
6
BIAS CKT.
COMPENSATION
(WHEN REQUIRED)
A
V
≈
5X
A
≈
6000X
A
V
≈
30X
INPUT
+
200
μ
A
200
μ
A
1.35mA
8mA
(NOTE 5)
0mA
(NOTE 7)
V+
OUTPUT
V-
STROBE
C
C
OFFSET
NULL
CA3130
NOTES:
6. Totalsupplyvoltage(forindicatedvoltagegains)=15Vwithinput
terminals biased so that Terminal 6 potential is +7.5V above Ter-
minal 4.
7. Total supply voltage (for indicated voltage gains) = 15V with out-
put terminal driven to either supply rail.
FIGURE 1. BLOCK DIAGRAM OF THE CA3130 SERIES
22.5
GATE VOLTAGE (TERMINALS 4 AND 8) (V)
O
17.5
20
12.5
15
10
7.5
2.5
5
0
2.5
7.5
5
10
15
12.5
17.5
0
SUPPLY VOLTAGE: V+ = 15, V- = 0V
T
A
= 25
C
LOAD RESISTANCE = 5k
500
1k
2k
FIGURE 2. VOLTAGE TRANSFER CHARACTERISTICS OF
CMOS OUTPUT STAGE
CA3130, CA3130A
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參數(shù)描述 |
|---|---|
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