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參數(shù)資料
| 型號： | CA3130AE |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 運動控制電子 |
| 英文描述： | 15MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output |
| 中文描述： | OP-AMP, 5000 uV OFFSET-MAX, 15 MHz BAND WIDTH, PDIP8 |
| 文件頁數(shù)： | 7/15頁 |
| 文件大?。?/td> | 654K |
| 代理商： | CA3130AE |
7
o
Power-Supply Considerations
Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B show the
CA3130 connected for both dual-and single-supply
operation.
Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q
8
and Q
12
are driven
increasingly positive with respect to ground, current flow
through Q
12
(from the negative supply) to the load is
increased and current flow through Q
8
(from the positive
supply) decreases correspondingly. When the gate terminals
of Q
8
and Q
12
are driven increasingly negative with respect
to ground, current flow through Q
8
is increased and current
flow through Q
12
is decreased accordingly.
Single-supply Operation: Initially, let it be assumed that the
value of R
L
is very high (or disconnected), and that the input-
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
across Q
8
and Q
12
are of equal magnitude. Figure 20 shows
typical quiescent supply-current vs supply-voltage for the
CA3130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage-transfer characteristics (see Figure 2). If either
Q
8
or Q
12
are swung out of their linear regions toward cut-off
(a non-linear region), there will be a corresponding reduction
in supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q
12
is completely cut off and the supply-current to
series-connected transistors Q
8
, Q
12
goes essentially to zero.
The two preceding stages in the CA3130, however, continue
to draw modest supply-current (see the lower curve in Figure
20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming R
L
=
∞
by pulling the
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2k
) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q
8
must now supply quiescent current to both R
L
and transistor Q
12
, it should be apparent that under these
conditions the supply-current must increase as an inverse
function of the R
L
magnitude. Figure 22 shows the voltage-
drop across PMOS transistor Q
8
as a function of load
current at several supply voltages. Figure 2 shows the
voltage-transfer characteristics of the output stage for
several values of load resistance.
Wideband Noise
From the standpoint of low-noise performance
considerations, the use of the CA3130 is most
advantageous in applications where in the source resistance
of the input signal is on the order of 1M
or more. In this
case, the total input-referred noise voltage is typically only
23
μ
V when the test-circuit amplifier of Figure 7 is operated
at a total supply voltage of 15V. This value of total input-
referred noise remains essentially constant, even though the
value of source resistance is raised by an order of
magnitude. This characteristic is due to the fact that
reactance of the input capacitance becomes a significant
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
SHIFT vs OPERATING LIFE
FIGURE 6A. DUAL POWER SUPPLY OPERATION
FIGURE 6B. SINGLE POWER SUPPLY OPERATION
FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLE
POWER SUPPLY OPERATION
T
A
= 125
o
C FOR TO-5 PACKAGES
7
6
5
4
3
2
1
0
500
1000
1500
2000
2500
3000 3500
4000
O
TIME (HOURS)
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
0
3
2
8
4
7
6
R
L
Q
8
Q
12
CA3130
+
-
V+
V-
3
2
8
4
7
6
R
L
Q
8
Q
12
CA3130
+
-
V+
CA3130, CA3130A
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| CA3130AM | 功能描述:IC OP AMP 15MHZ BIMOS 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
| CA3130AM96 | 功能描述:IC OP AMP 15MHZ BIMOS 8-SOIC RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
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| CA3130AMZ96 | 功能描述:運算放大器 - 運放 W/ANNEAL OPAMP 15MHZ LWBIAS 0 03NA COMP RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| CA3130AS | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Analog IC |
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