
4
Schematic Diagram
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages. Terminal 8 can
be used both for phase compensation and to strobe the
output stage into quiescence. When Terminal 8 is tied to the
negative supply rail (Terminal 4) by mechanical or electrical
means, the output potential at Terminal 6 essentially rises to
the positive supply-rail potential at Terminal 7. This condition
of essentially zero current drain in the output stage under the
strobed “OFF” condition can only be achieved when the
ohmic load resistance presented to the amplifier is very high
(e.g.,when the amplifier output is used to drive CMOS digital
circuits in Comparator applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
6
, Q
7
) working into a mirror-pair of bipolar
transistors (Q
9
, Q
10
) functioning as load resistors together
with resistors R
3
through R
6
. The mirror-pair transistors also
function as a differential-to-single-ended converter to provide
base drive to the second-stage bipolar transistor (Q
11
). Offset
nulling, when desired, can be effected by connecting a
100,000
potentiometer across Terminals 1 and 5 and the
potentiometer slider arm to Terminal 4. Cascade-connected
PMOS transistors Q
2
, Q
4
are the constant-current source for
the input stage. The biasing circuit for the constant-current
source is subsequently described. The small diodes D
5
3
2
1
8
4
6
7
Q
1
Q
2
Q
4
D
1
D
2
D
3
D
4
Q
3
Q
5
D
5
D
6
D
7
D
8
Q
9
Q
10
Q
6
Q
7
5
Z
1
8.3V
INPUT STAGE
R
3
1k
R
4
1k
R
6
1k
R
5
1k
NON-INV.
INPUT
INV.-INPUT
+
-
R
1
40k
5k
R
2
BIAS CIRCUIT
CURRENT SOURCE FOR
Q
6
AND Q
7
“CURRENT SOURCE
LOAD” FOR Q
11
V+
OUTPUT
OUTPUT
STAGE
Q
8
Q
12
V-
Q
11
SECOND
STAGE
OFFSET NULL
COMPENSATION
STROBING
(NOTE 5)
NOTE:
5. Diodes D
5
through D
8
provide gate-oxide protection for MOSFET input stage.
CA3130, CA3130A