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參數(shù)資料
| 型號： | CA3098E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | Programmable Schmitt Trigger with Memory, Dual Input Precision Level Detector |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDIP8 |
| 文件頁數(shù)： | 4/12頁 |
| 文件大小： | 229K |
| 代理商： | CA3098E |
4
General Description of Circuit Operation
When the signal input voltage of the CA3098 is equal to or
less than the “l(fā)ow” reference voltage (LR), current flows from
an external power supply through a load connected to
Terminal 3 (“sink” output). This condition is maintained until
the signal input voltage rises to or exceeds the “high”
reference voltage (HR), thereby effecting a change in the
state of the flip-flop (memory) such that the output stage
interrupts current flow in the external load. This condition, in
turn, is maintained until such time as the signal again
becomes equal to or less than the “l(fā)ow” reference voltage.
The CA3098 comparator is unique in that it contains circuit
provisions to permit programmability. This feature provides
flexibility to the designer to optimize quiescent power
consumption, input circuit characteristics, hysteresis, and
additionally permits independent control of the comparator,
namely, pulsing, strobing, keying, squelching, etc.
Programmability is accomplished by means of the bias
current (I
BIAS
) supplied to Terminal 2.
An auxiliary means of controlling the magnitude of load
current flow at Terminal 3 is provided by “sinking” current into
when connected as a simple hysteresis switch (Schmitt
trigger).
2
6
5
CA3098
I
O
R
L
E
O
V+ = 12V
DC
7
8
1
“LOW” REF. = 4V
“HIGH” REF. = 8V
4
INPUT
SIGNAL
E
IN
120k
R
B
SEQUENCE
INPUT SIGNAL
LEVEL
OUTPUT VOLTAGE (V)
(TERMINAL 3)
1
4
≥
E
IN
> 0
0
2
8
≥
E
IN
> 4
0
3
E
IN
> 8
12
2
8
≥
E
IN
> 4
12
1
4
≥
E
IN
> 0
0
3
FIGURE 1. BASIC HYSTERESIS SWITCH (SCHMITT
TRIGGER) AND RESULTANT OUTPUT STATES
Metallization Mask Layout
Dimensions in parentheses are in millimeters and are derived
from the basic inch dimensions as indicated. Grid graduations
are in mils (10
-3
inch).
The layout represents a chip when it is part of the wafer. When
the wafer is cut into chips, the cleavage angles are 57
o
instead
of 90
o
with respect to the face of the chip. Therefore, the
isolated chip is actually 7mils (0.17mm) larger in both
dimensions.
60
50
40
30
20
10
0
61
0
10
20
30
40
50
58
63 (1.600)
66 (1.676)
CA3098
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