Page 193
C8051F060/1/2/3
A
DVANCD
Advanced
Information
17.1.
Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to the digital
peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port pins are allocated in
order starting with P0.0 and continue through P3.7 (on the C8051F060/2) or P2.7 (on the C8051F061/3) if necessary.
The digital peripherals are assigned Port pins in a priority order which is listed in Figure 17.3, with UART0 having
the highest priority and CNVSTR2 having the lowest priority.
17.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to a logic 1 in
the Crossbar configuration registers XBR0, XBR1, XBR2, and XBR3, shown in Figure 17.5, Figure 17.6,
Figure 17.7, and Figure 17.8. For example, if the UART0EN bit (XBR0.2) is set to a logic 1, the TX0 and RX0 pins
will be mapped to P0.0 and P0.1 respectively. Because UART0 has the highest priority, its pins will always be
mapped to P0.0 and P0.1 when UART0EN is set to a logic 1. If a digital peripheral’s enable bits are not set to a
logic 1, then its ports are not accessible at the Port pins of the device. Also note that the Crossbar assigns pins to all
Figure 17.3. Priority Crossbar Decode Table
PIN I/O
TX0
0
G
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
RX0
G
SCK
G
G
MISO
G
G
MOSI
G
G
NSS
G
G
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
SDA
G
G G G G G
SCL
G
G G G G G
TX1
G
G G G G G G G
RX1
G
G G G G G G G
CEX0
G
G G G G G G G G G
CEX1
G
G G G G G G G G G
CEX2
G
G G G G G G G G G
CEX3
G
G G G G G G G G G
CEX4
G
G G G G G G G G G
CEX5
G
G G G G G G G G G
ECI
G G G G G G G G G G G G G G G G G
ECI0E: XBR0.6
CP0
G G G G G G G G G G G G G G G G G G
CP0E: XBR0.7
CP1
G G G G G G G G G G G G G G G G G G G
CP1E: XBR1.0
CP2
G G G G G G G G G G G G G G G G G G G G
CP2E: XBR3.3
T0
G G G G G G G G G G G G G G G G G G G G G
T0E: XBR1.1
/INT0
G G G G G G G G G G G G G G G G G G G G G G
INT0E: XBR1.2
T1
T1E: XBR1.3
/INT1
G G G G G G G G G G G G G G G G G G G G G G G G
INT1E: XBR1.4
T2
G G G G G G G G G G G G G G G G G G G G G G G G G
T2E: XBR1.5
T2EX
G G G G G G G G G G G G G G G G G G G G G G G G G G
T2EXE: XBR1.6
T3
G G G G G G G G G G G G G G G G G G G G G G G G G G G
T3E: XBR3.0
T3EX
G G G G G G G G G G G G G G G G G G G G G G G G G G G G
T3EXE: XBR3.1
T4
T4E: XBR2.3
T4EX
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
T4EXE: XBR2.4
/SYSCLK
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
SYSCKE: XBR1.7
CNVSTR2
G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G G
CNVSTE2: XBR3.2
A
A
A
A
A
A
A
A
C
C
C
C
C
C
XBR2.2
XBR0.[5:3]
UART0EN:
SPI0EN:
UART1EN:
PCA0ME:
Crossbar Register Bits
XBR0.2
XBR0.1
XBR0.0
SMB0EN:
P0
P1
P2
P3