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參數(shù)資料
| 型號： | 534AB000359DG |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 0K |
| 描述： | IC CLK XO QUAD FREQUENCY 8SMD |
| 應用說明： | Frequency Margining using the SI534 |
| 標準包裝： | 50 |
| 系列： | Si534 |
| 類型： | 振蕩器 - 晶體 |
| 頻率： | 167.33MHz，173.37MHz，193.77MHz，194.89MHz |
| 電源電壓： | 1.71 V ~ 3.63 V |
| 電流 - 電源： | 111mA |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 8-SMD，無引線 |
| 包裝： | 托盤 |
| 供應商設備封裝： | 8-SMD |
| 安裝類型： | 表面貼裝 |
| 其它名稱： | Q4733547A |
Si534
Rev. 1.3
3
Powerup Time4
tOSC
——
10
ms
Settling Time After FS[1:0]
Change
tFRQ
Both FS[1] and FS[0] changing
simultaneously
——
20
ms
Table 3. CLK± Output Levels and Symmetry
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
LVPECL Output Option1
VO
mid-level
VDD – 1.42
—
VDD – 1.25
V
VOD
swing (diff)
1.1
—
1.9
VPP
VSE
swing (single-ended)
0.55
—
0.95
VPP
LVDS Output Option2
VO
mid-level
1.125
1.20
1.275
V
VOD
swing (diff)
0.5
0.7
0.9
VPP
CML Output Option2
VO
2.5/3.3 V option mid-level
—
VDD – 1.30
—
V
1.8 V option mid-level
—
VDD – 0.36
—
V
VOD
2.5/3.3 V option swing (diff)
1.10
1.50
1.90
VPP
1.8 V option swing (diff)
0.35
0.425
0.50
VPP
CMOS Output Option3
VOH
IOH =32mA
0.8 x VDD
—
VDD
V
VOL
IOL =32mA
—
0.4
V
Rise/Fall time (20/80%)
tR, tF
LVPECL/LVDS/CML
—
350
ps
CMOS with CL =15pF
—
1
—
ns
Symmetry (duty cycle)
SYM
LVPECL:
VDD – 1.3 V
(diff)
LVDS:
1.25 V (diff)
CMOS:
VDD/2
45
—
55
%
Notes:
1. 50
to V
DD – 2.0 V.
2. Rterm = 100 (differential).
3. CL = 15 pF
Table 2. CLK± Output Frequency Characteristics (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Notes:
1. See Section 3. "Ordering Information" on page 7 for further details.
2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.
3. Selectable parameter specified by part number.
4. Time from powerup or tristate mode to fO.
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