參數(shù)資料
型號(hào): BS62LV4008TCG55
廠商: BRILLIANCE SEMICONDUCTOR, INC.
英文描述: Very Low Power/Voltage CMOS SRAM 512K X 8 bit
中文描述: 非常低功率/電壓CMOS SRAM的為512k × 8位
文件頁(yè)數(shù): 4/10頁(yè)
文件大小: 373K
代理商: BS62LV4008TCG55
Revision 1.1
Jan. 2004
4
R0201-BS62LV4008
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”O(jiān)FF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
BSI
BS62LV4008
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
Input Pulse Levels
Vcc / 0V
Input Rise and Fall Times
1V/ns
Input and Output
Timing Reference Level
0.5Vcc
Output Load
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
PARAMETER
NAME
DESCRIPTION
UNIT
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Read Cycle Time
55
--
--
70
--
--
ns
Address Access Time
--
--
55
--
--
70
ns
Chip Select Access Time
--
--
55
--
--
70
ns
Output Enable to Output Valid
--
--
30
--
--
35
ns
Chip Select to Output Low Z
10
--
--
10
--
--
ns
Output Enable to Output in Low Z
10
--
--
10
--
--
ns
Chip Deselect to Output in High Z
--
--
30
--
--
35
ns
Output Disable to Output in High Z
--
--
25
--
--
30
ns
Data Hold from Address Change
10
--
--
10
--
--
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
t
OH
t
AA
D
OUT
ADDRESS
t
OH
MIN.
TYP.
MAX.
(Vcc = 3.0~3.6V)
MIN.
TYP.
MAX.
(Vcc = 2.7~3.6V)
CYCLE TIME : 55ns
CYCLE TIME : 70ns
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