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參數(shù)資料
| 型號： | ATF1504ASVL-20JC44 |
| 廠商： | ATMEL CORP |
| 元件分類： | PLD |
| 英文描述： | Low-voltage, Complex Programmable Logic Device |
| 中文描述： | EE PLD, 20 ns, PQCC44 |
| 封裝： | PLASTIC, MS-018AC, LCC-44 |
| 文件頁數(shù)： | 6/21頁 |
| 文件大小： | 462K |
| 代理商： | ATF1504ASVL-20JC44 |
ATF1504ASZ
6
Figure 1.
ATF1504AS Macrocell
Programmable Pin-Keeper Option for
Inputs and I/Os
The ATF1504AS offers the option of programming all input
and I/O pins so that pin keeper circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low level.
This circuitry prevents unused input and I/O lines from
floating to intermediate voltage levels, which cause unnec-
essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.
Input Diagram
Speed/Power Management
The ATF1504AS has several built-in speed and power
management features. The ATF1504AS contains circuitry
that automatically puts the device into a low power stand-
by mode when no logic transitions are occurring. This not
only reduces power consumption during inactive periods,
but also provides a proportional power savings for most
applications running at system speeds below 50 MHz. This
feature may be selected as a design option.
I/O Diagram
To further reduce power, each ATF1504AS macrocell has
a Reduced Power bit feature. This feature allows individual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504ASs also have an optional power down mode.
In this mode, current drops to below 10 mA. When the
power down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power down
option is selected in the design source file. When enabled,
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| ATF1504ASVL-20JC68 | Low-voltage, Complex Programmable Logic Device |
| ATF1504ASL-20 | High performance Complex Programmable Logic Device |
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| ATF1504ASL-20AC44 | Circular Connector; MIL SPEC:MIL-C-5015 E/F/R; Body Material:Metal; Series:MS3101R; Number of Contacts:9; Connector Shell Size:20; Connecting Termination:Solder; Circular Shell Style:Cable Receptacle; Body Style:Straight |
| ATF1504ASL-20JC44 | ER 2C 2#8 SKT RECP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1504ASVL-20JC68 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JC84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JI44 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JI68 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| ATF1504ASVL-20JI84 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 64 MACROCELL 3.3V 20NS IND TEMP RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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