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參數(shù)資料
| 型號(hào)： | ATF1500ABV-15JI |
| 廠商： | Atmel |
| 文件頁(yè)數(shù)： | 4/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 15NS LOW VOLT PLCC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 系列： | ATF15xx |
| 可編程類型： | 系統(tǒng)內(nèi)可編程（最少 10,000 次編程/擦除循環(huán)） |
| 最大延遲時(shí)間 tpd(1)： | 15.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 5.25 V |
| 宏單元數(shù)： | 32 |
| 輸入/輸出數(shù)： | 32 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
| 其它名稱： | ATF1500ABV15JI |
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0723K–PLD–6/05
ATF1500ABV
22. Power-up Reset
The ATF1500ABV’s registers are designed to reset during power-up. At a point delayed slightly
from V
CC crossing VRST, all registers will be reset to the low state. As a result, the registered out-
put state will always be low on power-up.
This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
CC actually rises in the system, the following conditions are
required:
1.
The V
CC rise must be monotonic.
2.
Signals from which clocks are derived must remain stable during T
PR.
3.
After T
PR occurs, all input and feedback setup times must be met before driving the
clock signal high.
23. Power-down Mode
The ATF1500ABV includes an optional pin-controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply cur-
rent is reduced to less than 10 A. During power-down, all output data and internal logic states
are latched and held. Therefore, all registered and combinatorial output data remain valid. Any
outputs that were in a High-Z state at the onset of power-down will remain at High-Z. During
power-down, all input signals except the power-down pin are blocked. Input and I/O hold latches
remain active to ensure that pins do not float to indeterminate levels, further reducing system
power. The power-down pin feature is enabled in the logic design file. Designs using the power-
down pin may not use the PD pin logic array input. However, all other PD pin macrocell
resources may still be used, including the buried feedback and foldback product term array
inputs.
24. Register Preload
The ATF1500ABV’s registers are provided with circuitry to allow loading of each register with
either a high or a low. This feature will simplify testing since any state can be forced into the reg-
isters to control test sequencing. A JEDEC file with preload is generated when a source file with
preload vectors is compiled. Once downloaded, the JEDEC file preload sequence will be done
automatically when vectors are run by any approved programmers. The preload mode is
enabled by raising an input pin to a high voltage level. Contact Atmel PLD Applications for PRE-
LOAD pin assignments, timing and voltage requirements.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ATF1500ABVL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500ABVL-25AC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500ABVL-25JC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High- Performance EE PLD |
| ATF1500AL | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:High Performance E2 PLD |
| ATF1500AL-20AC | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD 32 MACROCELL LOW-PWR 5V-20NS RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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