參數(shù)資料
型號(hào): ATAM893T-TKS
廠商: Atmel
文件頁(yè)數(shù): 33/98頁(yè)
文件大?。?/td> 0K
描述: IC MON TIRE-PRESS ATARX9X SER
標(biāo)準(zhǔn)包裝: 830
系列: MARC4
核心處理器: MARC4
芯體尺寸: 4-位
速度: 4MHz
連通性: SSI(2 線,3 線)
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 4KB(4K x 8)
程序存儲(chǔ)器類型: EEPROM
EEPROM 大?。?/td> 64 x 16
RAM 容量: 256 x 4
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 6.5 V
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 20-SOIC(0.209",5.30mm 寬)
包裝: 管件
39
4680C–4BMCU–01/05
ATAM893-D
5.3.2.2
Timer 2 Output Modes
The signal at the timer output is generated via modulator 2. In the toggle mode, the compare
match event toggles the output T2O. For high resolution duty cycle modulation 8 bits or 12 bits
can be used to toggle the output. In the duty cycle burst modulator modes the DCG output is
connected to T2O and switched on and off either by the toggle flipflop output or the serial data
line of the SSI. Modulator 2 also has 2 modes to output the content of the serial interface as Bi-
phase or Manchester code.
The modulator output stage can be configured by the output control bits in the T2M2 register.
The modulator is started with the start of the shift register (SIR = 0) and stopped either by carry-
ing out a shift register stop (SIR = 1) or compare match event of stage 1 (CM1) of Timer 2. For
this task, Timer 2 mode 3 must be used and the prescaler has to be supplied with the internal
shift clock (SCL).
Figure 5-14. Timer 2 Modulator Output Stage
5.3.2.3
Timer 2 Output Signals
Timer 2 Output Mode 1
Toggle Mode A: A Timer 2 compare match toggles the output flip-flop (M2)
→T2O
Figure 5-15. Interrupt Timer/Square Wave Generator – the Output Toggles with Each Edge
Compare Match Event
Toggle
RES/SET
Bi-phase/
Manchester
modulator
T2TOP
T2OS2, 1, 0
T2M2
T2O
M2
S1
S2
S3
Modulator 3
RE
FE
OMSK
SSI
CONTROL
TOG2
SO
DCGO
4
0
123
4
01
23
4
012
3
0
1
Input
Counter 2
T2R
Counter 2
CMx
INT4
T2O
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