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參數(shù)資料
| 型號： | ATA555814M01-PP |
| 廠商： | Atmel Corp. |
| 英文描述： | 1 kbit R/W IDIC with Deterministic Anticollision |
| 中文描述： | 1千比特讀/寫的確定性防撞投資業(yè)務 |
| 文件頁數(shù)： | 9/42頁 |
| 文件大?。?/td> | 557K |
| 代理商： | ATA555814M01-PP |
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9
4681C–RFID–09/05
ATA5558 [Preliminary]
2.8
Tag Configuration Register
The internal tag configuration register holds a shadow copy of the configuration settings stored
in the system memory’s block 63. It is refreshed after every POR cycle (RF field on), Reset to
Ready or Write to block 63.
Figure 2-7.
Configuration Register
3.
Transmission Protocol
The transmission protocol defines the mechanism to exchange commands and data between
the interrogator and the tags. In all but the Public and EAS Mode, the interrogator has complete
control over the communication flow – all data transmission being synchronized to interrogator
commands and the interrogator field clock – “Interrogator Talks First” (ITF) principle. This means
that a tag does not transmit data, unless it has received and properly decoded an interrogator
command.
The protocol is based on an exchange of
commands from the interrogator to the tag (Downlink mode)
and response from the tag to the interrogator (Uplink mode)
ITF =Interrogator Talks First Mode
PM = Public Mode
EAS = Electrical Article Surveillance
NRZ = Non Return to Zero
Notes:
(1) If master key = 6hex then all test modes are ignored and password protection enabled
(2) If DDR = 1 and master key = 6hex or 9hex then data rate = fast, otherwise slow
R = reserved for future use, should be set to 0
x = don't care state
L
a4 a3
p2
a2 a1 a0
RF/2(n+1)
...LSB
1
MSB...
31 30 29 28
1
0
3
2
0
7
6
0
5
0
4
15 14 13 12
n4 n3 n2 n1 n0
19 18 17 16
23 22 21 20
11 10 9 8
0
27 26 25 24
R R
1
0
0 =
Reserved
Max. Block
0 =Unlocked
1 =Locked
Uplink
Data Bit Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
= 16 bit
= 32 bit
= 48 bit
= 64 bit
= 80 bit
= 96 bit
= 40 bit
= 56 bit
1 =
Downlink CRC check
mandatory
TagID
Length
Downlink Data Rate
(DDR)
(2)
R
0
0
1
1
0
1
0
1
= Manchester
= NRZ (Direct Coding)
= FDX-B (Biphase)
= Reserved
Uplink
Encoding
SOF
Preamble
Length
( bit periods )
= 1
= 2
.
.
= 8
0
0
.
.
1
0
0
.
.
1
0
1
.
.
1
Master Key
(1)
Lock Bit
p1 p0
x
0
1
0
1
1
= ITF
= PM
= EAS
Operating
Mode
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PDF描述 |
|---|---|
| ATA555814-PAE | 1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555814-PP | 1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815-DDT | 1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815-DDW | 1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815M01-DDT | 1 kbit R/W IDIC with Deterministic Anticollision |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ATA555814-PAE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555814-PP | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815C-PP | 功能描述:外圍驅動器與原件 - PCI ATA555815C-PP Transponder RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| ATA555815-DDT | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815-DDW | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
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