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參數(shù)資料
| 型號： | ATA555814M01-PP |
| 廠商： | Atmel Corp. |
| 英文描述： | 1 kbit R/W IDIC with Deterministic Anticollision |
| 中文描述： | 1千比特讀/寫的確定性防撞投資業(yè)務(wù) |
| 文件頁數(shù)： | 28/42頁 |
| 文件大?。?/td> | 557K |
| 代理商： | ATA555814M01-PP |
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28
4681C–RFID–09/05
ATA5558 [Preliminary]
7.4
Write Single Block
The Write Single Block command only effects tag(s) which have been previously been put in the
Selected state. It performs the programming of a specific block address with a 32-bit block of
data and associated lock bit. For password protected memory blocks the LoginWrite command
has to be executed first, otherwise the programming will fail and an error code will be returned.
Memory blocks which have a
1
in the lock bit are locked and cannot be written. The command
protocol includes downlink CRC (CRC_d) which is used to check the downlink address and
data. This CRC_d can be mandatory or optional depending on the state of bit 10 of the configu-
ration register. If set to
1
, the CRC_d must always be included and correct for the data
programming to take place. If set to
0
, the CRC_d is optional i.e. it is only checked if the CRC
data is present.
On receiving the Write command, and if necessary checking the CRC_d, the tag will start the
EEPROM programming sequence. The maximum EEPROM program time per block (including
the lock bit) is 6 ms. This programming cycle includes an automatic read verification phase
which makes sure that the data has been programmed securely thus ensuring satisfactory long
term data retention. To signal the completion of a successful programming cycle, the tag returns
a single SOF pattern.
If for any reason the programming of the data block fails, the tag will generate the corresponding
error code. The error code bits are dual pattern coded (see
Figure 3-1 on page 10
) and pre-
ceded by a SOF pattern. An attempt to write to a locked block address or a downlink CRC error
causes an immediate abort of the programming cycle followed by the transmission of the corre-
sponding error response. In the case of an EEPROM data verification failure, the error response
is returned after the completion of the programming cycle.
Note:
1. The downlink CRC (CRC_d) must be appended if bit 10 of the configuration register =
1
, oth-
erwise it is optional.
Table 7-5.
Command
Interrogator Command Parameters
Parameter 1
Parameter 2
CRC (optional)
Read =
00 01
Start Block Address
End Block Address
CRC_d (Start Block Addr +
End Block Addr)
4 bit
6 bits (MSB first)
6 bits (MSB first)
16 bits (MSB first)
Table 7-6.
SOF
Tag Response
Data
CRC
Start of Frame
Multiple Data Blocks
CRC_u (Start Block Addr +
End Block Addr + [CRC_d*] + Data)
3 .. 10-bit period
((EndAddr – StartAddr + 1)
×
32) bits
(MSB first)
16 bits (MSB first)
Table 7-7.
Command
Write Single Block
=
00 01
Interrogator Command Parameters
Parameter 1
Parameter 2
Parameter 3
CRC
(1)
CRC_d (Block Addr
+ Lock + Data)
Block Address
0
+ Lock bit
Write Data
4 bits
6 bits (MSB first)
2 bits
32 bits (MSB first)
16 bits (MSB first)
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ATA555814-PAE | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
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| ATA555815-DDT | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
| ATA555815-DDW | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1 kbit R/W IDIC with Deterministic Anticollision |
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