參數(shù)資料
型號: AT91FR4042-CI
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: AT91 ARM Thumb Microcontrollers
中文描述: 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PBGA121
封裝: 10 X 10 MM, 1.20 MM HEIGHT, BGA-121
文件頁數(shù): 12/22頁
文件大?。?/td> 195K
代理商: AT91FR4042-CI
12
AT91FR4042
2648D–ATARM–03/04
During boot, the EBI must be configured with correct number of standard wait states. As
an example, five standard wait states are required when the microcontroller is running at
66 MHz.
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to
their respective supplies by the shortest route. The Flash memory powers-on in read
mode. Command sequences are used to place the device in other operating modes,
such as program and erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility,
enabling the reset operation to adapt to the application. When this input is at a logic high
level, the memory is in its standard operating mode; a low level on this input halts the
current memory operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a
program cycle is in progress, an attempted read of the last word written will return the
complement of the written data on I/O7. An open-drain NBUSY output pin provides
another method of detecting the end of a program or erase cycle. This pin is pulled low
while program and erase cycles are in progress and is released at the completion of the
cycle. A toggle bit feature provides a third means of detecting the end of a program or
erase cycle.
The Flash memory is divided into 4 sectors for erase operations.
The device has the capability to protect data stored in the 8K words boot block sector.
Once the data protection for this sector is enabled, the data in the sector cannot be
changed while input levels lie between ground and V
DDIO
. The address range of the boot
block is 00000h to 01FFFh
The user can override the boot block programing lockout by applying a 12 V input signal
to the RESET pin while performing a chip erase, sector erase or word programing
operation.
A 4-byte command sequence (Enter Single Pulse Program Mode) allows the device to
be written to directly, using single pulses on the write control lines. This mode (Single-
pulse Programming) is exited by powering down the device or by pulsing the NRSTF pin
low for a certain duration
(1)
and then bringing it back to V
DDIO
.
The following hardware features protect against inadvertent programming of the Flash
memory:
V
DDIO
Sense – if V
DDIO
is below a certain level
(1)
, the program function is inhibited.
V
DDIO
Power-on Delay – once V
DDIO
has reached the V
DDIO
sense level, the device
will automatically time out for a certain duration
(1)
before programming.
Program Inhibit – holding any one of OE low, CE high or WE high inhibits program
cycles.
Noise Filter – pulses of less than a certain duration
(1)
on the WE or CE inputs will not
initiate a program cycle.
See the AT49BV4096A 4-megabit (256K x 16/512K x 8) Single 2.7 volt Flash Memory
Datasheet for further details on Flash operation and electrical characteristics.
Note:
1. Defined in the AT49BV4096A Flash Memory Datasheet, Atmel lit° 1618.
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