參數(shù)資料
型號(hào)： AT91FR4042-CI
廠商： ATMEL CORP
元件分類(lèi)： 微控制器/微處理器
英文描述： AT91 ARM Thumb Microcontrollers
中文描述： 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PBGA121
封裝： 10 X 10 MM, 1.20 MM HEIGHT, BGA-121
文件頁(yè)數(shù)： 11/22頁(yè)
文件大?。?/td> 195K
代理商： AT91FR4042-CI
11
AT91FR4042
2648D–ATARM–03/04
The BMS pin is multiplexed with the I/O line P24 that can be programmed after reset like
any standard PIO line.
Remap Command
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91FR4042 uses
a remap command that enables switching between the boot memory and the internal
primary SRAM bank addresses. The remap command is accessible through the EBI
User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing
a remap command is mandatory if access to the other external devices (connected to
chip selects 1 to 7) is required. The remap operation can only be changed back by an
internal reset or an NRST assertion.
Abort Control
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI
is asserted when accessing an undefined address in the EBI address space.
No abort is generated when reading the internal memory or by accessing the internal
peripherals, whether the address is defined or not.
External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and
can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte,
half-word and word aligned accesses.
For each of these banks, the user can program:
Number of wait states
Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device is too long in releasing the bus)
Data bus width (8-bit or 16-bit)
With a 16-bit wide data bus, the user can program the EBI to control one 16-bit
device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-
bit memory (Byte Write Access Mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device in
the case of single-clock cycle access.
In the AT91FR4042, the External Bus Interface connects internally to the Flash memory.
Flash Memory
The 4-Mbit Flash memory is organized as 262144 words of 16 bits each. The Flash
memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A18.
The address, data and control signals, except the Flash memory enable, are internally
interconnected. The user should connect the Flash memory enable (NCSF) to one of
the active-low chip selects on the EBI; NCS0 must be used if the Flash memory is to be
the boot memory. In addition, if the Flash memory is to be used as boot memory, the
BMS input must be pulled down externally in order for the processor to perform correct
16-bit fetches after reset.
Table 3.
Boot Mode Select
BMS
Boot Memory
1
External 8-bit memory on NCS0
0
External 16-bit memory on NCS0
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