參數(shù)資料
型號(hào): AT91FR4042-CI
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: AT91 ARM Thumb Microcontrollers
中文描述: 32-BIT, FLASH, 70 MHz, RISC MICROCONTROLLER, PBGA121
封裝: 10 X 10 MM, 1.20 MM HEIGHT, BGA-121
文件頁數(shù): 10/22頁
文件大小: 195K
代理商: AT91FR4042-CI
10
AT91FR4042
2648D–ATARM–03/04
To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles
before the rising edge of NRST. For normal operation, the NTRI pin must be held high
during reset by a resistor of up to 400 k
.
NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.
JTAG/ICE Debug
ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The
TDI, TDO, TCK and TMS pins are dedicated to this debug function and can be con-
nected to a host computer via the external ICE interface. In ICE Debug Mode, the
ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller.
This is not fully IEEE1149.1 compliant.
Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes
the internal 32-bit address bus and defines three address spaces:
Internal memories in the four lowest megabytes
Middle space reserved for the external devices (memory or peripherals) controlled
by the EBI
Internal peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
Internal Memories
The AT91FR4042 microcontroller integrates 256K bytes of internal SRAM. It is 32 bits
wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit)
accesses are supported and are executed within one cycle. Fetching either Thumb or
ARM instructions is supported, and internal memory can store two times as many
Thumb instructions as ARM instructions.
The SRAM is mapped at address 0x0 (after the Remap command), allowing
ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software.
Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the
microcontroller performance and minimizes system power consumption. The 32-bit bus
increases the effectiveness of the use of the ARM instruction set and the processing of
data that is wider than 16 bits, thus making optimal use of the ARM7TDMI advanced
performance.
Being able to dynamically update application software in the 256-Kbyte SRAM adds an
extra dimension to the AT91FR4042.
The AT91FR4042 also integrates a 4-Mbit Flash memory that is accessed via the Exter-
nal Bus Interface. All data, address and control lines, except for the Chip Select signal,
are connected within the device.
Boot Mode Select
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in nonvolatile memory after the reset. The input level on the
BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the
type of boot memory (see Table 1 on page 3).
If the embedded Flash memory is to be used as boot memory, the BMS input must be
pulled down externally and NCS0 must be connected to NCSF externally.
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