參數(shù)資料
型號: AT83C51RB2XXX-SLSIL
廠商: ATMEL CORP
元件分類: 微控制器/微處理器
英文描述: Microcontroller
中文描述: 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 8/81頁
文件大?。?/td> 1082K
代理商: AT83C51RB2XXX-SLSIL
9
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Oscillators
Overview
One oscillator is available for CPU:
OSC used for high frequency (3 MHz to 40 MHz)
In order to optimize the power consumption and the execution time needed for a specific
task, an internal prescaler feature has been implemented between the selected oscilla-
tor and the CPU.
Registers
Table 4.
Clock Reload Register
Reset Value = 1111 1111b
Not bit addressable
Prescaler Divider
A hardware RESET puts the prescaler divider in the following state:
CKRL = FFh: F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard C51 feature)
KS signal selects OSC: F
CLK OUT
= F
OSC
Any value between FFh down to 00h can be written by software into CKRL register
in order to divide frequency of the selected oscillator:
CKRL = 00h: minimum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/1020 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/510 (X2 Mode)
CKRL = FFh: maximum frequency
F
CLK CPU
= F
CLK PERIPH
= F
OSC
/2 (Standard Mode)
F
CLK CPU
= F
CLK PERIPH
= F
OSC
(X2 Mode)
F
CLK CPU
and F
CLK PERIPH
In X2 mode:
In X1 mode:
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
Bit
Number
Bit
Mnemonic Description
7:0
CKRL
Clock Reload Register: Prescaler value
F
CPU
F
=
CLKPERIPH
F
255
2
CKRL
F
255
(
)
×
----------------------------------------------
=
F
CPU
F
=
CLKPERIPH
4
CKRL
(
)
×
-----------------------------------------------
=
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