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參數(shù)資料
| 型號： | AT83C51RB2XXX-SLSIL |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 61/81頁 |
| 文件大?。?/td> | 1082K |
| 代理商： | AT83C51RB2XXX-SLSIL |
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62
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 45.
WDTPRG Register
WDTPRG - Watchdog Timer Out Register (0A7h)
Reset Value = XXXX X000
WDTDuringPower-down
and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in
Power-down mode the user does not need to service the WDT. There are 2 methods of
exiting Power-down mode: by a hardware reset or via a level activated external inter-
rupt which is enabled prior to entering Power-down mode. When Power-down is exited
with hardware reset, servicing the WDT should occur as normal, whenever the
T8xc51Rx2 is reset. Exiting Power-down with an interrupt is significantly different. The
interrupt is held low long enough for the oscillator to stabilize. When the interrupt is
brought high, the interrupt is serviced. To prevent the WDT from resetting the device
while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of power-down,
it is better to reset the WDT just before entering power-down.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the
T8xc51Rx2 while in Idle mode, the user should always set up a timer that will periodi-
cally exit Idle, service the WDT, and re-enter Idle mode.
7
6
5
4
3
2
1
0
-
-
-
-
-
S2
S1
S0
Bit
Number
Bit
Mnemonic Description
7
-
Reserved
The value read from this bit is undetermined. Do not try to set this bit.
6
-
5
-
4
-
3
-
2
S2
WDT Time-out select bit 2
1
S1
WDT Time-out select bit 1
0
S0
WDT Time-out select bit 0
S2
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
Selected Time-out
(2
14
- 1) machine cycles, 16. 3 ms @ F
osc
=12 MHz
(2
15
- 1) machine cycles, 32.7 ms @ F
osc
=12 MHz
(2
16
- 1) machine cycles, 65. 5 ms @ F
osc
=12 MHz
(2
17
- 1) machine cycles, 131 ms @ F
osc
=12 MHz
(2
18
- 1) machine cycles, 262 ms @ F
osc
=12 MHz
(2
19
- 1) machine cycles, 542 ms @ F
osc
=12 MHz
(2
20
- 1) machine cycles, 1.05 s @ F
osc
=12 MHz
(2
21
- 1) machine cycles, 2.09 s @ F
osc
=12 MHz
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