- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄381493 > AT83C51RB2XXX-SLSIL (ATMEL CORP) Microcontroller PDF資料下載
參數(shù)資料
| 型號： | AT83C51RB2XXX-SLSIL |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontroller |
| 中文描述： | 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 60/81頁 |
| 文件大?。?/td> | 1082K |
| 代理商： | AT83C51RB2XXX-SLSIL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁當(dāng)前第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁
61
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. Therefore, the user must
reset the WDT at least every 16383 machine cycles. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
CLK PERIPH
, where T
CLK PERIPH
= 1/F
CLK
PERIPH
. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
7
counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ F
osc
= 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 44.
Table 44.
WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT83C51RB2XXX-SLSIM | Microcontroller |
| AT83C51RC2XXX-3CSCM | Microcontroller |
| AT83C51RC2XXX-3CSIM | Microcontroller |
| AT83C51RC2XXX-RLTIL | Microcontroller |
| AT83C51RC2XXX-RLTIM | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT83C51RB2XXX-SLSIM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:Microcontroller |
| AT83C51RC2 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT83C51RC2-3CSUL | 制造商:IRF 制造商全稱:International Rectifier 功能描述:High Performance 8-bit Microcontroller |
| AT83C51RC2-3CSUM | 制造商:IRF 制造商全稱:International Rectifier 功能描述:High Performance 8-bit Microcontroller |
| AT83C51RC2-RLTUL | 制造商:IRF 制造商全稱:International Rectifier 功能描述:High Performance 8-bit Microcontroller |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。