參數(shù)資料
型號(hào)： AT83C51RB2XXX-SLSIL
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： Microcontroller
中文描述： 8-BIT, MROM, 40 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁(yè)數(shù)： 11/81頁(yè)
文件大?。?/td> 1082K
代理商： AT83C51RB2XXX-SLSIL
12
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 5.
CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
7
6
5
4
3
2
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
Do not set this bit.
6
WDX2
Watchdog clock
(This control bit is validated when the CPU clock X2 is set;
when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
PCAX2
Programmable Counter Array clock
(This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4
SIX2
Enhanced UART clock (Mode 0 and 2)
(This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3
T2X2
Timer 2 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2
T1X2
Timer 1 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1
T0X2
Timer 0 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0
X2
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte
(HCB).
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