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參數(shù)資料
| 型號： | AT80C51RD2 |
| 廠商： | Atmel Corp. |
| 英文描述： | ER 6C 3#16 3#8 SKT RECP BOX |
| 中文描述： | 80C51的高性能ROM的8位微控制器 |
| 文件頁數(shù)： | 60/81頁 |
| 文件大?。?/td> | 1082K |
| 代理商： | AT80C51RD2 |
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61
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Hardware Watchdog
Timer
The WDT is intended as a recovery method in situations where the CPU may be sub-
jected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer
Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable
the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location
0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator
is running and there is no way to disable the WDT except through reset (either hardware
reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH
pulse at the RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR
location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH
and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it
reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. Therefore, the user must
reset the WDT at least every 16383 machine cycles. To reset the WDT the user must
write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an output RESET pulse
at the RST-pin. The RESET pulse duration is 96 x T
CLK PERIPH
, where T
CLK PERIPH
= 1/F
CLK
PERIPH
. To make the best use of the WDT, it should be serviced in those sections of code
that will periodically be executed within the time required to prevent a WDT reset.
To have a more powerful WDT, a 2
7
counter has been added to extend the Time-out
capability, ranking from 16 ms to 2s @ F
osc
= 12 MHz. To manage this feature, refer to
WDTPRG register description, Table 44.
Table 44.
WDTRST Register
WDTRST - Watchdog Reset Register (0A6h)
Reset Value = XXXX XXXXb
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in
sequence.
7
6
5
4
3
2
1
0
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT83C51RB2 | 80C51 High Performance ROM 8-bit Microcontroller |
| AT83C51RC2 | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSCM | Microcontroller |
| AT80C51RD2-3CSIM | Microcontroller |
| AT80C51RD2-RLTIL | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT80C51RD2_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2_09 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSCM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSIM | 功能描述:IC MCU 8051 5V SPI 20MHZ 40-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲器容量:32KB（32K x 8） 程序存儲器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
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