參數(shù)資料
型號(hào): AT80C51RD2
廠商: Atmel Corp.
英文描述: ER 6C 3#16 3#8 SKT RECP BOX
中文描述: 80C51的高性能ROM的8位微控制器
文件頁數(shù): 59/81頁
文件大?。?/td> 1082K
代理商: AT80C51RD2
60
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Figure 22.
Power-down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external
interrupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal
RAM content.
Note:
If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence
is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and
idle mode is not entered.
Table 43 shows the state of ports during idle and power-down modes.
Note:
1. Port 0 can force a 0 level. A "one" will leave port floating.
INT1
INT0
XTAL
Power-down Phase
OscillatoR Restart Phase
Active Phase
Active Phase
Table 43.
State of Ports
Mode
Program Memory
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
1
1
Port Data
(1)
Port Data
Port Data
Port Data
Idle
External
1
1
Floating
Port Data
Address
Port Data
Power-down
Internal
0
0
Port Dat
(1)
Port Data
Port Data
Port Data
Power-down
External
0
0
Floating
Port Data
Port Data
Port Data
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