參數(shù)資料
型號(hào): AT80C51RD2
廠商: Atmel Corp.
英文描述: ER 6C 3#16 3#8 SKT RECP BOX
中文描述: 80C51的高性能ROM的8位微控制器
文件頁數(shù): 54/81頁
文件大小: 1082K
代理商: AT80C51RD2
55
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Keyboard Interface
The T8xc51Rx2 implement a keyboard interface allowing the connection of a 8 x n
matrix keyboard. It is based on 8 inputs with programmable interrupt capability on both
high or low level. These inputs are available as alternate function of P1 and allow to exit
from idle and power-down modes.
The keyboard interfaces with the C51 core through 3 special function registers: KBLS,
the Keyboard Level Selection register (Table 42), KBE, The Keyboard Interrupt Enable
register (Table 41), and KBF, the Keyboard Flag register (Table 40).
Interrupt
The keyboard inputs are considered as 8 independent interrupt sources sharing the
same interrupt vector. An interrupt enable bit (KBD in IE1) allows global enable or dis-
able of the keyboard interrupt (see Figure 20). As detailed in Figure 21 each keyboard
input has the capability to detect a programmable level according to KBLS.x bit value.
Level detection is then reported in interrupt flags KBF.x that can be masked by software
using KBE.x bits.
This structure allow keyboard arrangement from 1 x n to 8 x n matrix and allows usage
of P1 inputs for other purpose.
Figure 20.
Keyboard Interface Block Diagram
Figure 21.
Keyboard Input Circuitry
Power Reduction Mode
P1 inputs allow exit from idle and power-down modes as detailed in Section “Power-
down Mode”, page 59.
P1:x
KBE.x
KBF.x
KBLS.x
0
1
V
CC
Internal Pull-up
P1.0
Keyboard Interface
Interrupt Request
KBD
IE1
Input Circuitry
P1.1
Input Circuitry
P1.2
Input Circuitry
P1.3
Input Circuitry
P1.4
Input Circuitry
P1.5
Input Circuitry
P1.6
Input Circuitry
P1.7
Input Circuitry
KBDIT
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