參數(shù)資料
型號: AT80C51RD2
廠商: Atmel Corp.
英文描述: ER 6C 3#16 3#8 SKT RECP BOX
中文描述: 80C51的高性能ROM的8位微控制器
文件頁數(shù): 44/81頁
文件大小: 1082K
代理商: AT80C51RD2
45
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 31.
BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
Reset Value = XXX0 0000b
Not bit addressable
7
6
5
4
3
2
1
0
-
-
-
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
BRR
Baud Rate Run Control bit
Cleared to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
3
TBCK
Transmission Baud rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
2
RBCK
Reception Baud Rate Generator Selection bit for UART
Cleared to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
1
SPD
Baud Rate Speed Control bit for UART
Cleared to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
0
SRC
Baud Rate Source select bit in Mode 0 for UART
Cleared to select F
OSC
/12 as the Baud Rate Generator (F
CLK PERIPH
/6 in X2
mode).
Set to select the internal Baud Rate Generator for UARTs in mode 0.
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