參數(shù)資料
型號(hào)： AT80C51RD2
廠商： Atmel Corp.
英文描述： ER 6C 3#16 3#8 SKT RECP BOX
中文描述： 80C51的高性能ROM的8位微控制器
文件頁數(shù)： 42/81頁
文件大?。?/td> 1082K
代理商： AT80C51RD2
43
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 29.
T2CON Register
T2CON - Timer 2 Control Register (C8h)
Reset Value = 0000 0000b
Bit addressable
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Description
7
TF2
Timer 2 overflow Flag
Must be cleared by software.
Set by hardware on Timer 2 overflow, if RCLK=0 and TCLK=0.
6
EXF2
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if
EXEN2 = 1.
When set, causes the CPU to vector to Timer 2 interrupt routine when Timer 2
interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down
counter mode (DCEN=1)
5
RCLK
Receive Clock bit for UART
Cleared to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.
4
TCLK
Transmit Clock bit for UART
Cleared to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3
EXEN2
Timer 2 External Enable bit
Cleared to ignore events on T2EX pin for Timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is
detected, if Timer 2 is not used to clock the serial port.
2
TR2
Timer 2 Run control bit
Cleared to turn off Timer 2.
Set to turn on Timer 2.
1
C/T2#
Timer/Counter 2 select bit
Cleared for timer operation (input from internal clock system: F
).
Set for counter operation (input from T2 input pin, falling edge trigger). Must be
0 for clock out mode.
0
CP/RL2#
Timer 2 Capture/Reload bit
If RCLK = 1 or TCLK = 1, CP/RL2# is ignored and timer is forced to auto-reload
on Timer 2 overflow.
Cleared to auto-reload on Timer 2 overflows or negative transitions on T2EX pin
if EXEN2 = 1.
Set to capture on negative transitions on T2EX pin if EXEN2 = 1.
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