參數(shù)資料
型號(hào)： AT80C51RD2
廠商： Atmel Corp.
英文描述： ER 6C 3#16 3#8 SKT RECP BOX
中文描述： 80C51的高性能ROM的8位微控制器
文件頁(yè)數(shù)： 24/81頁(yè)
文件大小： 1082K
代理商： AT80C51RD2
25
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 11.
CMOD Register
CMOD - PCA Counter Mode Register (D9h)
Reset Value = 00XX X000b
Not bit addressable
The CMOD register includes three additional bits associated with the PCA (see
Figure 11 and Table 11).
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in
the CCON SFR) to be set when the PCA timer overflows.
The CCON register contains the run control bit for the PCA and the flags for the PCA
timer (CF) and each module (see Table 12).
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by
clearing this bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an
interrupt will be generated if the ECF bit in the CMOD register is set. The CF bit can
only be cleared by software.
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1,
etc.) and are set by hardware when either a match or a capture occurs. These flags
can only be cleared by software.
7
6
5
4
3
2
1
0
CIDL
WDTE
-
-
-
CPS1
CPS0
ECF
Bit
Number
Bit
Mnemonic
Description
7
CIDL
Counter Idle Control
Cleared to program the PCA Counter to continue functioning during idle Mode.
Set to program PCA to be gated off during idle.
6
WDTE
Watchdog Timer Enable
Cleared to disable Watchdog Timer function on PCA Module 4.
Set to enable Watchdog Timer function on PCA Module 4.
5
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2
CPS1
PCA Count Pulse Select
CPS1
CPS0 Selected PCA input
0
0
Internal clock f
CLK PERIPH/6
0
1
Internal clock f
CLK PERIPH/2
1
0
Timer 0 Overflow
1
1
External clock at ECI/P1.2 pin (max rate = f
CLK PERIPH/4
)
1
CPS0
0
ECF
PCA Enable Counter Overflow Interrupt
Cleared to disable CF bit in CCON to inhibit an interrupt.
Set to enable CF bit in CCON to generate an interrupt.
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