參數(shù)資料
型號(hào): AT80C51RD2
廠商: Atmel Corp.
英文描述: ER 6C 3#16 3#8 SKT RECP BOX
中文描述: 80C51的高性能ROM的8位微控制器
文件頁數(shù): 12/81頁
文件大小: 1082K
代理商: AT80C51RD2
13
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Dual Data Pointer
Register
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 6) that allows the program
code to switch between them (Refer to Figure 4).
Figure 4.
Use of Dual Pointer
Table 6.
AUXR1 Register
AUXR1- Auxiliary Register 1(0A2h)
Reset Value: XXXX XXXX0b
Not bit addressable
Note:
1. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
0
7
DPTR0
DPTR1
7
6
5
4
3
2
1
0
-
-
-
-
GF3
0
-
DPS
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
-
Reserved
4
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3
GF3
This bit is a general purpose user flag.
2
0
Always cleared
(1)
.
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0
DPS
Data Pointer Selection
Cleared to select DPTR0.
Set to select DPTR1.
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