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參數(shù)資料
| 型號(hào)： | AT80C51RD2 |
| 廠商： | Atmel Corp. |
| 英文描述： | ER 6C 3#16 3#8 SKT RECP BOX |
| 中文描述： | 80C51的高性能ROM的8位微控制器 |
| 文件頁數(shù)： | 11/81頁 |
| 文件大?。?/td> | 1082K |
| 代理商： | AT80C51RD2 |
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12
AT80C51RD2/AT83C51Rx2
4113A–8051–09/02
Table 5.
CKCON0 Register
CKCON0 - Clock Control Register (8Fh)
Reset Value = 0000 000’HCB.X2’b (see Hardware Config Byte)
Not bit addressable
7
6
5
4
3
2
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Number
Bit
Mnemonic
Description
7
-
Reserved
Do not set this bit.
6
WDX2
Watchdog clock
(This control bit is validated when the CPU clock X2 is set;
when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
PCAX2
Programmable Counter Array clock
(This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
4
SIX2
Enhanced UART clock (Mode 0 and 2)
(This control bit is validated when the
CPU clock X2 is set; when X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
3
T2X2
Timer 2 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
2
T1X2
Timer 1 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1
T0X2
Timer 0 clock
(This control bit is validated when the CPU clock X2 is set; when
X2 is low, this bit has no effect).
Cleared to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
0
X2
CPU clock
Cleared to select 12 clock periods per machine cycle (STD mode) for CPU and
all the peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the
individual peripherals "X2" bits.
Programmed by hardware after Power-up regarding Hardware Config Byte
(HCB).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AT83C51RB2 | 80C51 High Performance ROM 8-bit Microcontroller |
| AT83C51RC2 | 80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSCM | Microcontroller |
| AT80C51RD2-3CSIM | Microcontroller |
| AT80C51RD2-RLTIL | Microcontroller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT80C51RD2_05 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2_08 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2_09 | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSCM | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:80C51 High Performance ROM 8-bit Microcontroller |
| AT80C51RD2-3CSIM | 功能描述:IC MCU 8051 5V SPI 20MHZ 40-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:80C 標(biāo)準(zhǔn)包裝:9 系列:87C 核心處理器:8051 芯體尺寸:8-位 速度:40/20MHz 連通性:UART/USART 外圍設(shè)備:POR，WDT 輸入/輸出數(shù):32 程序存儲(chǔ)器容量:32KB（32K x 8） 程序存儲(chǔ)器類型:OTP EEPROM 大小:- RAM 容量:256 x 8 電壓 - 電源 (Vcc/Vdd):4.5 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:0°C ~ 70°C 封裝/外殼:40-DIP（0.600"，15.24mm） 包裝:管件 |
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