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參數(shù)資料
| 型號(hào)： | AT49BV080T-20CI |
| 廠商： | ATMEL CORP |
| 元件分類： | DRAM |
| 英文描述： | 8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| 中文描述： | 1M X 8 FLASH 2.7V PROM, 200 ns, PBGA42 |
| 封裝： | 8 X 14 MM, 1 MM PITCH, PLASTIC, CBGA-42 |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 201K |
| 代理商： | AT49BV080T-20CI |
be performed. Please refer to the Command Definitions
table.
BOOT BLOCK LOCKOUT DETECTION:
A software
method is available to determine if programming of the
boot block section is locked out. When the device is in the
software product identification mode (see Software Prod-
uct Identification Entry and Exit sections) a read from ad-
dress location 00002H will show if programming the boot
block is locked out. If the data on I/O0 is low, the boot
block can be programmed; if the data on I/O0 is high, the
program lockout feature has been activated and the block
cannot be programmed. The software product identifica-
tion exit code should be used to return to standard opera-
tion.
BOOT BLOCK PROGRAMMING LOCKOUT OVER-
RIDE:
The user can override the boot block programming
lockout by taking the RESET pin to 12 + 0.5 volts. By doing
this, protected boot block data can be altered through a
chip erase, or byte programming. When the RESET pin is
brought back to TTL levels the boot block programming
lockout feature is again active.
PRODUCT IDENTIFICATION:
The product identification
mode identifies the device and manufacturer as Atmel. It
may be accessed by hardware or software operation. The
hardware operation mode can be used by an external pro-
grammer to identify the correct programming algorithm for
the Atmel product.
For details, see Operating Modes (for hardware operation)
or Software Product Identification. The manufacturer and
device code is the same for both modes.
DATA POLLING:
The AT49BV/LV080 features DATA
polling to indicate the end of a program cycle. During a
program cycle an attempted read of the last byte loaded
will result in the complement of the loaded data on I/O7.
Once the program cycle has been completed, true data is
valid on all outputs and the next cycle may begin. DATA
polling may begin at any time during the program cycle.
TOGGLE BIT:
In addition to DATA polling, the
AT49BV/LV080 provides another method for determining
the end of a program or erase cycle. During a program or
erase operation, successive attempts to read data from
the device will result in I/O6 toggling between one and
zero. Once the program cycle has completed, I/O6 will
stop toggling and valid data will be read. Examining the
toggle bit may begin at any time during a program cycle.
RDY/BUSY:
An open drain READY/BUSY output pin pro-
vides another method of detecting the end of a program or
erase operation. RDY/BUSY is actively pulled low during
the internal program and erase cycles and is released at
the completion of the cycle. The open drain connection al-
lows for OR - tying of several devices to the same
RDY/BUSY line.
RESET:
A RESET input pin is provided to ease some
system applications. When RESET is at a logic high level,
the device is in its standard operating mode. A low level on
the RESET input halts the present device operation and
puts the outputs of the device in a high impedance state.
If the RESET pin makes a high to low transition during a
program or erase operation, the operation may not be suc-
cessfully completed, and the operation will have to be re-
peated after a high level is applied to the RESET pin.
When a high level is reasserted on the RESET pin, the
device returns to the read or standby mode, depending
upon the state of the control inputs. By applying a 12V +
0.5V input signal to the RESET pin the boot block array
can be reprogrammed even if the boot block lockout fea-
ture has been enabled (see Boot Block Programming
Lockout Override section).
HARDWARE DATA PROTECTION:
Hardware features
protect against inadvertent programs to the
AT49BV/LV080 in the following ways: (a) V
CC
sense: if
V
CC
is below 1.8V (typical), the program function is inhib-
ited. (b) Program inhibit: holding any one of OE low, CE
high or WE high inhibits program cycles. (c) Noise filter:
pulses of less than 15 ns (typical) on the WE or CE inputs
will not initiate a program cycle.
Device Operation
(Continued)
AT49BV/LV080
3
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PDF描述 |
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| AT49BV080T-20RC | 8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
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| AT49BV080T-20TC | 8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AT49BV080T-20RC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| AT49BV080T-20RI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| AT49BV080T-20TC | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| AT49BV080T-20TI | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:8-Megabit 1M x 8 Single 2.7-volt Battery-Voltage Flash Memory |
| AT49BV1024A | 制造商:ATMEL 制造商全稱:ATMEL Corporation 功能描述:1-megabit (64K x 16) 3-volt Only Flash Memory |
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