參數(shù)資料
型號(hào): AT27C520-70SI
廠商: ATMEL CORP
元件分類(lèi): DRAM
英文描述: ECONOLINE: RY-S_DCP - Internal SMD Technology- 1kVDC Isolation- Short Circuit Protection: Current Limit- UL94V-0 Package Material- Regulated Output- No External Components Required- Efficiency to 63%
中文描述: 64K X 8 OTPROM, 70 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOIC-20
文件頁(yè)數(shù): 7/10頁(yè)
文件大?。?/td> 126K
代理商: AT27C520-70SI
AT27C520
7
AC Programming Characteristics
T
A
= 25
±
5
°
C, V
CC
= 6.5
±
0.25V, OE/V
PP
= 13.0
±
0.25V
Notes:
1. V
CC
must be applied simultaneously or before OE/V
PP
and removed simultaneously or after OE/V
PP
.
2. Program Pulse width tolerance is 50
μ
sec
±
5%.
3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven
— see timing diagram.
Atmel’s 27C520 Integrated Product Identification Code
Symbol
Parameter
(1)
Test Conditions
Limits
Units
Min
Max
t
ALE
t
LAS
t
LAH
t
LP
t
OES
t
OEH
t
DS
t
DH
t
PW
t
VR
t
VCS
t
OE
t
DFP
t
AS
t
AH
t
PRT
Address Latch Enable Width
Input Rise and Fall Times
(10% to 90%) 20 ns
Input Pulse Levels
0.45V to 2.4V
Input Timing Reference Level
0.8V to 2.0V
Output Timing Reference Level
0.8V to 2.0V
500
ns
Latched Address Setup Time
100
ns
Latched Address Hold Time
100
ns
ALE Low to OE/V
PP
High Voltage Delay
OE/V
PP
Setup Time
OE/V
PP
Hold Time
Data Setup Time
2
μ
s
2
μ
s
2
μ
s
2
μ
s
Data Hold Time
2
μ
s
ALE Program Pulse Width
(2)
47.5
52.5
μ
s
OE/V
PP
Recovery Time
V
CC
Setup Time
2
μ
s
2
μ
s
Data Valid from OE/V
PP
OE/V
PP
High to Output Float Delay
(3)
Address Setup Time
150
ns
0
130
ns
2
μ
s
Address Hold Time
0
μ
s
OE/V
PP
Pulse Rise Time During Programming
50
ns
Codes
Pins
Hex
Data
A8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
Manufacturer
0
0
0
0
1
1
1
1
0
1E
Device Type
1
1
0
0
1
1
1
0
1
9D
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